Chip Designing for ASIC/ FPGA Design engineers and Students

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Verilog - RTL (Register Transfer Level) examples

Verilog is a programming language designed to code hardware at register transfer level. The digital hardware consists of concurrent and sequential events. A synchronous digital circuit is modeled with following considerations:
<> A circuit consists of sequential & parallel events.
<> Interim results are stored in registers.
<> Registers are generally implemented as D Flip Flops.
<> Data is transferred between registers which are synchronous to each other.
Verilog Tutorial is covered online here.

Verilog operators - Building blocks of Verilog. Follow topics in verilog tutorial to learn the language.  

Verilog Initial Statements -  Used in Test benches for generating stimulus (clocks, resets, etc).

Conditional Statements - ‘IF-ELSE’ statement and use in ‘always’ block. ‘case’ statement

Synchronous Counters. Implementation example.

Complete Verilog ‘readmemh’ code to read hex values in a test-bench.

Functions and its call in verilog tutorial.

Verilog file read write operations.
Verilog testbench example. More examples are presented online under Verilog tutorial.

Verilog Binary to Gray Code conversion example.

Verilog code for clock domain crossing.
Half-adder, Full-adder, Tri-state buffer implementation in verilog. Testbench to validate half-adder, full-adder and tri-state buffer.

Verilog counter enable logic.

Verilog difference between blocking and non-blocking statements.

Readmemb click here

Shift micro operations - Logical Shift Right (LSR) verilog code and simulation results. LSR discussion here. Logical Shift left (LSL)
verilog code and simulation results. LSL discussion here. Circular Shift Right (CSR) verilog code, results, discussion. Circular Shift Right (CSR) verilog code, simulation results and discussion.

Random number generation in test-bench and use of $fdisplay.

Memory - synchronous RAM implementation and test-bench

Resources

Clock Domain Crossing Discussion with
rtl & testbench example.

Rate change (asynchronous) FIFO design and fifo depth calculation.

Half-adder, Full-adder, 4-bit binary adder , adder-subtractor circuit, overflow with rtl & testbench. Binary Multiplier, Parity error TT
Arithmetic, logical, shift micro-operations. Stack organization, LIFO, RPN discussion.
VHDL rtl - Synchronous flip-flop, latch, shim to improve timing and counter example

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels.
Digital design Interview questions.
FPGA Interview. FPGA flow.
Guide to Graduate studies in US

LTE - Long Term Evolution topics from here

Digital Logic fundamentals topics @ fcd

Digital basics tutorial
Binary number discussion, 1 and 2 complement discussion,
Binary arithmetic, Signed Magnitude, overflow, examples
Gray coding, Binary coded digital (BCD) coding, BCD addition
Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates
Discussion of Boolean Algebra with examples.
Duality Principle, Huntington Postulates, Theorems of Boolean Algebra - discussion with examples,
Boolean Functions,
Canonical and Standard Forms, Minterms and Maxterms
Sum of Minterms, Product of Maxterms or Canonical Forms,
Karnaugh map or K-map discussion 2, 3, ,4 and 5 var’s
Prime Implicant and Gate level minimization examples.

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Interview Questions. Main, FPGA, Digital Fundamentals

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