Verilog code to implement clock domain crossing, rate change asynchronous fifo depth calculation, half-adder, full-adder, tristate buffer, binary to gray conversion, $readmemh, file read write, $display, $fdisplay, $random, testbench. Python glob.glob module, sys.argv, commandline, stripoff, classes and global variable. 2,3 ,4 ,5 variable Karnaugh k-map tutorial, xor, xnor gate truth-table,Boolean Algebra, Duality Principle, Huntington Postulates, Canonical and Standard Forms, Minterms and Maxterms, SOM, Prime Implicant and Gate level minimization.

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Topics @TYH :- 4G LTE Tutorial, GVIM editor, Smart-Phone, Cloud Computing

RTL Design engineers

FORUM

Computer Organization.
Memory Organization.
Cache Organization.
Interrupt controller.

Verilog RTL.

Verilog is a programming language specifically designed to program hardware at Register Transfer Level (RTL). Link to Verilog Tutorial or Verilog examples home page:

Verilog operators. Initial statements and ‘always’ block code. Refer System Verilog always_ff and always_comb from here.

Blocking vs. Non-blocking statements. Parameters passing, defparam & localparam. Synthesis constant propagation. ‘IF-ELSE’, FOR loop, ‘case’ statement and synchronous counters,

$Readmemh code to read hex values, function Declaration, file read write ‘readmemh’ in verilog test-bench (tb). Verilog code for Clock Crossing. (setup, hold, meta), digital signal logic values Z, X, U, H, L, W.

Verilog testbench example for clock domain crossing. Binary to Gray code conversion code. Inter/Intra delay.

Half-adder, Full-adder, Tri-state buffer inverter, bus and tb. Digital counter enable/disable logic in rtl and tb

Shift micro-ops, Random number and use of $fdisplay.
Arithmetic shift uops
Memory implementation, test-bench & FPGA RAM.
Signed addition test-bench. Microoperations in rtl discussion.
System Verilog functions, always_comb vs always_ff
ASIC/FPGA synthesis topics. Synthesis constraints.

Resources
Digital design. Synthesis stages, syntax.
Clock Domain Crossing Discussion with
rtl & testbench example.
Rate change(asynchronous) FIFO design and fifo depth calculation.
Half-adder, Full-adder, 4-bit binary adder , adder-subtractor circuit, overflow with rtl & testbench. Binary Multiplier, Parity error TT
Arithmetic, logical, shift micro-operations. Stack organization, LIFO, RPN discussion.
VHDL rtl - Synchronous flip-flop, latch, shim to improve timing and counter example. Events, transactions, delays. Signals and variables. RTL coding guidelines. ICG cell, Assertions, $assertk, levels. Chandle, alias, array, system verilog functions. Digital Interview questions. FPGA Interview. Nflow.
Guide to Graduate studies in US
Pipeline vs. Parallel processing.
Computer Organization, CPU, ALU, Memory
Apps layer.

Digital Logic fundamentals
Digital basics tutorial. Binary number discussion, 1 and 2 complement discussion, Binary arithmetic, Signed Magnitude, overflow, examples, signed addition.
Gray coding, Binary coded digital (BCD) coding, BCD addition
-7 tp +7 signed numbers.
Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates. Universal NAND Gate, AND gate from NAND gate, OR gate from universal NAND gate.
Discussion of Boolean Algebra with examples.
Duality Principle, Huntington Postulates, Theorems of Boolean Algebra - discussion with examples,
Boolean Functions,
Canonical and Standard Forms, Minterms and Maxterms
Sum of Minterms, Product of Maxterms or Canonical Forms,
Karnaugh map or K-map discussion 2 ex, 3, solved 3 var K-map Examples ,4 and 5 var’s. Prime Implicant and Gate level minimization examples.

Tech in your Hand
Smart phone high tech hardware
Hardware inside smart phones.
CPU, OS, RAM, Apps, Pixels, SD mem
Cloud computing Next Internet revolution.
Interrupt cntr VIC’s. Interrupt registers
4G UMTS LTE Tutorial
Long Term Evolution (LTE), data rates, Core Air and Radio networks, seamless mobility, Evolved Packet core (EPC), SAE etc.
Mobility Management Entity (MME),
Serving Gateway SGW.
Packet Data Network (PDN) SAE Gateway
Enhanced Packet Data Gateway (ePDG)
LTE Interfaces 2 ,3, X2 N X2AP
Multiple antenna techniques in 4G - AAS, MIMO, Diversity.
LTE Access tech, LTE PHY layer, Generic Frame structure, Generic Downlink frame MIMO control PCFICH, PHICH, PDCC, PDSCH and config, alternative frame
LTE vs CDMA LTE vs. WiMax, LTE mVoIP.

CMOS Introduction, Digital ASIC’s design process, Circuit parasitics, Stray capacitances, Crosstalk, Ground Bounce

Python.
Python is a scripting language based on Object Oriented Principles with extensive support for engineering requirements. Python examples

File read, ‘sys.argv’, classes, global variables functions,
File write, command line, classes in file writes, glob module
Python conditional statements, convert string to hexadecimal value, strip off white space and convert hex to signed values.
Advanced program to read file, filter text, conversion to HEX, conversion from Hexadecimal to Signed Magnitude
Advanced python code to cover UNIX shell commands, read lines from a text file, ‘sysargv’ command line operations, use of class and multiple functions.
Read binary files, Calling classes using main function, generate diamond pattern. Python error’s with complete code examples:- TypeError: __init__() takes exactly 2 arguments (1 given) TypeError: 'str' object is not callable
TypeError: not all arguments converted during string formatting. AttributeError: ** instance has no attribute **

Topics covered in Verilog RTL, Digital Design, Digital Basics, RF and Python.

Logical Shift Right code, Logical Shift left (LSL) code, Circular Shift Right (CSR) code and Circular Shift Right (CSR) code. (Verilog)

Verilog Tutorial :- Introduction, operators, initial, clk & rst, blk vs non blk, cond if, counter, file ops, read bin, for loop, functions, testbench, random, shift micro-ops, memory, generate, assertions.

gvim Editor GVIM Advance - regular expressions to delete empty lines, merge empty lines, drop blank characters, search numbers, search and replace, duplicate columns, revert changes in time, shell commands, make, reverse order of lines, markers, set syntax, spell check.

LTE cells, network. LTE cell search, cell identities & sync signals (primary and secondary). 2X2 MIMO, DL MIMO frame format 2x2, UL MIMO frame format 2x2. 4G LTE differences in FDD and TDD modes.
UMTS LTE Reference Signals. DMRS pilot demodulation, Inter Symbol Interference.
LTE HARQ Type I and Type II HARQ vs. ARQ

Computer Organization.
Computer Introduction. Building blocks - ALU, ACC, PC, Registers, Stack Pointer, IR, timing and control unit.
Memory Organization.
Cache memory, fully-associative cache, hardware architecture, match circuit, control circuit. Direct-mapped cache, main memory and discussion. Interrupt controller, Vectored Interrupt Controller. Interrupt registers

3D draw and render new, 2D, 2D to 3D, ARC, 3D semi-cylindrical, door, Edgeing, drawer, colors and render.

Android App Dev: Layout and Intent to load static html.

Cloud Computing
Inside Smart Phones