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Initial stmts IF-ELSE Case stms Readmemh Function Testbench Binary to Gray Clock Crossing Half-adder Full-adder Tristate buffer Adder tb Counter_enable Blocking Operators Shift LSR Random Nos Sync RAM Verilog Tutorial
Verilog Tutorial.
Digital Basics Tutorial.
Verilog Tutorial
Logical Shift left (LSL) verilog code and simulation results. LSL discussion here. Circular Shift Right (CSR) verilog code, results, discussion.
Circular Shift Right (CSR) verilog code, simulation results and discussion.
Random number and use of $fdisplay.
Memory implementation and test-bench
Evolved Packet Core (EPC) system architecture for all IP.Mobility Management Entity (MME),
Serving System (S) Architecture (A) Evolution (E) Gateway or Serving Gateway SGW.
Packet Data Network (PDN) SAE Gateway
Enhanced Packet Data Gateway (ePDG)
Multiple antenna techniques - MIMO, Adaptive antenna systems - AAS and Antenna diversity - AD
Examples to supplement Verilog Tutorial knowledge.  

Verilog Binary to Gray Code conversion example.
Verilog code for clock domain crossing.
Half-adder, Full-adder, Tri-state buffer implementation in verilog.
Verilog testbench to validate half-adder, full-adder and tri-state buffer.
Verilog counter enable logic.
Logical Shift Right (LSR) verilog code and simulation results. LSR discussion here.
Interview Questions.

Digital Design
FPGA’s
Digital Fundamentals
Micro-operations

Arithmetic microoperations
Logical microoperations
Shift micro-operations, Overflow Arithmetic