Chip Designing for ASIC/ FPGA Design engineers and Students

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Digital-logic Design...  Dream for many students… start learning front-end…

Topics @TYH :- 4G LTE Tutorial, Inside Smart-Phone, Cloud Computing

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Direct link to return to Verilog Tutorial
http://www.fullchipdesign.com/verilog_tutorial.htm

Verilog Tutorial

Introduction to Verilog RTL under Verilog tutorial.

Verilog Operators.

Initial Statements in verilog.

Clock and Reset generation discussion in Verilog Tutorial.

Blocking vs. Non-blocking Statements.

Conditional Statements & ‘always’ block.

Digital Logic fundamentals topics @ fcd

Digital basics tutorial
Binary number discussion, 1 and 2 complement discussion,
Binary arithmetic, Signed Magnitude, overflow, examples
Gray coding, Binary coded digital (BCD) coding, BCD addition
Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates
Discussion of Boolean Algebra with examples.
Duality Principle, Huntington Postulates, Theorems of Boolean Algebra - discussion with examples,
Boolean Functions,
Canonical and Standard Forms, Minterms and Maxterms
Sum of Minterms, Product of Maxterms or Canonical Forms,
Karnaugh map or K-map discussion 2, 3, ,4 and 5 var’s
Prime Implicant and Gate level minimization examples.

Logical Shift left (LSL) verilog code and simulation results. LSL discussion here. Circular Shift Right (CSR) verilog code, results, discussion.
Circular Shift Right (CSR) verilog code, simulation results and discussion.
Random number and use of $fdisplay.
Memory implementation and test-bench

Evolved Packet Core (EPC) system architecture for all IP.Mobility Management Entity (MME),
Serving System (S) Architecture (A) Evolution (E) Gateway or Serving Gateway SGW.
Packet Data Network (PDN) SAE Gateway
Enhanced Packet Data Gateway (ePDG)
Multiple antenna techniques - MIMO, Adaptive antenna systems - AAS and Antenna diversity - AD

LTE topics @ FCD

What is LTE? Key driving factors behind 4G technology.
LTE Data rates and comparison with 3G rates.
Difference between air, radio and core network..  

Media Gallery

Las Vegas
Grand Canyon
Alcatraz -the rock
San Francisco
Napa Valley
Los Angeles
17 Mile Drive
Golden Gate Bridge
Blog- Planning California Trip

Function declaration and call in Verilog RTL code.

Testbench example - complete code.

Generate random numbers and $fdisplay.

Shift micro-operations and use in rtl.

Memory - Synchronous RAM implementation.

Verilog Generate for memory instances.

Assertions in Verilog Introduction and few examples.

Parameters passing and Defparam statements.  

Counter Implementation.

File Operations - $fopen, $fclose, $fdisplay, $fscanf

Read binary or hex format files - $readmemh, $readmemb.

FOR Loop use under Verilog tutorial  examples.  

Examples to supplement Verilog Tutorial knowledge.  

Verilog Binary to Gray Code conversion example.
Verilog code for clock domain crossing.
Half-adder, Full-adder, Tri-state buffer implementation in verilog.
Verilog testbench to validate half-adder, full-adder and tri-state buffer.
Verilog counter enable logic.
Logical Shift Right (LSR) verilog code and simulation results. LSR discussion here.

Resources
Digital design resources
Clock Domain Crossing rtl & testbench.

Rate change FIFO design and fifo depth calculation.

Half-adder, Full-adder, 4-bit binary adder , adder-subtractor circuit,

Overflow with rtl & testbench.

Binary Multiplier,

Parity error TT,

Arithmetic, logical, shift micro-operations.

Stack organization, LIFO, RPN discussion.

RTL coding guidelines.

ICG cell, Assertions,  levels.

Interview questions.
FPGA Interview. FPGA flow. Guide to Graduate studies in US

Pipeline vs. Parallel processing.

Interview Questions.

Digital Design
FPGA’s
Digital Fundamentals

Micro-operations

Arithmetic microoperations
Logical microoperations
Shift micro-operations, Overflow Arithmetic

K-map - 2,3,4,5 var & Prime Implicant discussion

Arithmetic, logical and shift microoperations.

Binary to Gray code conversion

Readmemh, Readmemb. Random numbers

Memory Implementation - sync Ram and Testbench