Verilog Tutorial
This is a systematic section to provide details on Verilog rtl coding. Witihn fullchipdesign you can discover several pages to go deeper into
logic fundamentals.
- Foundation of RTL design.
- Introduction to Verilog RTL under Verilog tutorial.
- Verilog Operators.
- Very first
statements
in verilog. - Starting with a simple
test-bench
. - Introduction to
blocking
vs. non-blocking. - Logic
constructs
.- Conditional Statements & ‘always’ block.
- CASE statement implementation.
- Shift micro-
operations and use in rtl. - FOR Loop use under Verilog tutorial examples.
- Memory
instantiation
and validation. - Disucssion on Assertions.
- Parameters passing.
- Signed RTL Design.
Discuss another blog on verilog rtl examples here.