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Tri-state buffer discussion
Verilog RTL example for tri-state
// Tristate Buffer
module tristate_buffer(input_x, enable, output_x);
input input_x;
input enable;
output output_x;
assign output_x = enable? input_x : 'bz;
endmodule
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Output of above Tri-
-
input_x = 0, enable = 0, output_x = z
input_x = 1, enable = 0, output_x = z
input_x = 1, enable = 1, output_x = 1
input_x = 0, enable = 1, output_x = 0
Introduction to Verilog RTL
Verilog Operators.
Initial Statements in verilog.
Clock and Reset generation.
Blocking vs. Non-blocking Statements.
Conditional Statements & ‘always’ block.
Counter Implementation.
File Operations - $fopen, $fclose, $fdisplay, $fscanf
Read binary or hex format files - $readmemh, $readmemb.
FOR Loop use in verilog code example
Verilog Operators.
Initial Statements in verilog.
Clock and Reset generation.
Blocking vs. Non-
Conditional Statements & ‘always’ block.
Counter Implementation.
File Operations -
Read binary or hex format files -
FOR Loop use in verilog code example
Digital Logic fundamentals topics @ fcd
Digital basics tutorial
Binary number discussion, 1 and 2 complement discussion,
Binary arithmetic, Signed Magnitude, overflow, examples
Gray coding, Binary coded digital (BCD) coding, BCD addition
Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates
Discussion of Boolean Algebra with examples.
Duality Principle, Huntington Postulates, Theorems of Boolean Algebra - discussion with examples, Boolean Functions, Canonical and Standard Forms, Minterms and Maxterms
Sum of Minterms, Product of Maxterms or Canonical Forms,
Karnaugh map or K-map discussion 2, 3, ,4 and 5 var’s
Prime Implicant and Gate level minimization examples.
Digital basics tutorial
Binary number discussion, 1 and 2 complement discussion,
Binary arithmetic, Signed Magnitude, overflow, examples
Gray coding, Binary coded digital (BCD) coding, BCD addition
Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates
Discussion of Boolean Algebra with examples.
Duality Principle, Huntington Postulates, Theorems of Boolean Algebra -
Karnaugh map or K-
Prime Implicant and Gate level minimization examples.
Resources
Verilog RTL code examples for front-end chip design.
Digital Design Topics
Half-adder , full-adder ,
Adder-sub tractor
Stack Organization - LIFO, RPN
Parity Generation and error checking
Binary multiplier circuit.
CMOS introduction
Digital fundamentals -
RTL coding guidelines. ICG cell, Assertions, $assertkill, levels. Chandle
Pipeline vs. Parallel processing.
Verilog RTL code examples for front-
Digital Design Topics
Half-
Adder-
Stack Organization -
Parity Generation and error checking
Binary multiplier circuit.
CMOS introduction
Digital fundamentals -
RTL coding guidelines. ICG cell, Assertions, $assertkill, levels. Chandle
Pipeline vs. Parallel processing.
LTE - Long Term Evolution topics from here
Interview Questions. Main, FPGA, Digital Fundamentals