Home Verilog Digital Design Digital Basics Python RF Basics

Legal Disclaimer

Chip Designing for ASIC/ FPGA Design engineers and Students
FULLCHIPDESIGN
Digital-logic Design...  Dream for many students… start learning front-end…
Topics @TYH :- 4G LTE Tutorial, GVIM editor, Smart-Phone, Cloud Computing
FCD
Custom Search

Feedback ? Send it to admin@fullchipdesign.com or join me at fullchip@gmail.com

Legal Disclaimer

Previous.
Next.
Initial stmts IF-ELSE Case stms Readmemh Function Testbench Binary to Gray Clock Crossing Half-adder Full-adder Tristate buffer Adder tb Counter_enable Blocking Operators Shift LSR Random Nos Sync RAM Verilog Tutorial
Verilog Tutorial.
Digital Basics Tutorial.
Tri-state buffer logic discussion
Verilog RTL example for tri-state logic buffer. Also discussed below are the output results.
Tri-state buffer test-bench.
Tristate buffer, inverting tristate buffer symbol, truth table and on chip implementations bus, bidirectional IO port direction control.

// Tristate Buffer

module tristate_buffer(input_x, enable, output_x);

input input_x;

input enable;

output output_x;

assign output_x = enable? input_x : 'bz;

endmodule

-----------------------------------------------------

Output of above Tri-State Buffer code

-----------------------------------------------------

input_x = 0, enable = 0, output_x = z

input_x = 1, enable = 0, output_x = z

input_x = 1, enable = 1, output_x = 1

input_x = 0, enable = 1, output_x = 0

Full-adder.
Adder tb.

Tri-state buffer acts as a switch in digital circuit by isolating a signal path in a circuit. This switch can attain three logical states. The three states are 0, 1 and ‘Z’. The logical state 0 and 1 are possible when the switch is CLOSE. The logical value ‘Z’ or high impedance is attained when switch is OPEN. So when switch is open the input to tristate buffer is isolated from the circuit and output can be driven by some other logical path on a shared connection/bus.  

We will discuss tri-state logic with brief introduction followed by Verilog code to implement it at RTL level. Will also cover Inverting tristate buffer

Tristate Inv Tristate Bus
Interview Questions. Main, FPGA, Digital basics

Tristate buffer symbol, inverter and truth table

Tri-state buffer with ENA High is Switch open or Hi-Z circuit. Truth Table and symbol are discussed below. First implementation of truth table allows the output to go floating without attaining a high or low. This allows other devices connected on shared bus to drive the bus.

Tri state Buffer

In

ENA

Out

ENA

IN

OUT

0

0

0

0

1

1

1

0

Z

1

1

Z

Tri-state buffer with ENA low is switch open, Truth Table and symbol below:

ENA

IN

OUT

0

0

Z

0

1

Z

1

0

0

1

1

1

Tri state Buffer

In

ENA

Out

Inverting Tri-state buffer Truth Table, circuit and symbol below:

ENA

IN

OUT2

0

0

1

0

1

0

1

0

Z

1

1

Z

Tri state Buffer

In

ENA

Out2

Tri-state buffer acts as a switch in digital circuit by isolating a signal path in a circuit. This switch can attain three logical states. The three states are 0, 1 and ‘Z’. The logical state 0 and 1 are possible when the switch is CLOSE. The logical value ‘Z’ or high impedance is attained when switch is OPEN. So when switch is open the input to tristate buffer is isolated from the circuit and output can be driven by some other logical path on a shared connection/bus.  

Tristate buffers can be used for shared bus interfaces, bidirectional IOs and shared memory interfaces. These onchip implementations allows bi-directional IO’s to switch polarities from input to output. Also when used on external chip-memory interface, these can switch to floating or high Z outputs to allow other devices on the same shared bus to access same memory.

On chip implementations using tristate buffer.

Tri-state buffer with ENA low is Switch open or Hi-Z, Truth Table and symbol from here: The implementation in truth table allows the output to go floating without attaining a high or low. This allows other devices connected on shared bus to drive the bus. Tristate buffer interface to memory shared bus is next.

Tri-state buffer with ENA low is switch open, Truth Table below:

ENA

IN

OUT

0

0

Z

0

1

Z

1

0

0

1

1

1

Verilog code for tristate buffer.

How to use tristate buffer on shared memory interfaces
LTE - Long Term Evolution topics from here