Tri-state buffer logic discussion.

We will discuss tri-state logic with brief introduction followed by Verilog code to implement it at RTL level. Will also cover Inverting tristate buffer.

Tri-state buffer acts as a switch in digital circuit by isolating a signal path in a circuit. This switch can attain three logical states. The three states are 0, 1 and ‘Z’. The logical state 0 and 1 are possible when the switch is CLOSE. The logical value ‘Z’ or high impedance is attained when switch is OPEN. So when switch is open the input to tristate buffer is isolated from the circuit and output can be driven by some other logical path on a shared connection on a bus. Note an imporatant interview question.

Verilog RTL example for tri-state logic buffer. Also discussed below are the output results.

// Tristate Buffer

module tristate_buffer(input_x, enable, output_x);

input input_x;

input enable;

output output_x;

assign output_x = enable? input_x : 'bz;

endmodule

Tri-state buffer test-bench.

Output of above Tri-State Buffer code

input_x = 0, enable = 0, output_x = z

input_x = 1, enable = 0, output_x = z

input_x = 1, enable = 1, output_x = 1

input_x = 0, enable = 1, output_x = 0

Tristate buffer, inverting tristate buffer symbol, truth table and on chip implementations bus, bidirectional IO port direction control.

LTE - 4G Wireless Technology

Digital fundamentals.

Interview Questions.

On chip implementations using tristate buffer.

Tristate buffers can be used for shared bus interfaces, bidirectional IOs and shared memory interfaces. These onchip implementations allows bi-directional IO’s to switch polarities from input to output. Also when used on external chip-memory interface, these can switch to floating or high Z outputs to allow other devices on the same shared bus to access same memory.

Tri-state buffer with ENA low is Switch open or Hi-Z, Truth Table and symbol from hereThe implementation in truth table allows the output to go floating without attaining a high or low. This allows other devices connected on shared bus to drive the bus. Tristate buffer interface to memory shared bus is next.

Tristate buffer

Tristate buffer symbol, inverter and truth table.

Tri-state buffer with ENA High is Switch open or Hi-Z circuit. Truth Table and symbol are discussed below. First implementation of truth table allows the output to go floating without attaining a high or low. This allows other devices connected on shared bus to drive the bus.

Tristate buffer

Tutorials @fullchipdesign.com

Verilog Tutorial.

LTE Tutorial.

Memory Tutorial.

Tri-state buffer with ENA low is switch open, Truth Table and symbol below:

Tristate buffer

Tri-state buffer acts as a switch in digital circuit by isolating a signal path in a circuit. This switch can attain three logical states. The three states are 0, 1 and ‘Z’. The logical state 0 and 1 are possible when the switch is CLOSE. The logical value ‘Z’ or high impedance is attained when switch is OPEN. So when switch is open the input to tristate buffer is isolated from the circuit and output can be driven by some other logical path on a shared connection/bus.

Inverting Tri-state buffer Truth Table, circuit and symbol below:

Tristate buffer

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