Tri-state buffer acts as a switch in digital circuit by isolating a signal path in
a circuit. This switch can attain three logical states. The three states are 0, 1
and ‘Z’. The logical state 0 and 1 are possible when the switch is CLOSE. The logical
value ‘Z’ or high impedance is attained when switch is OPEN. So when switch is open
the input to tristate buffer is isolated from the circuit and output can be driven
by some other logical path on a shared connection/bus.
We will discuss tri-state logic with brief introduction followed by Verilog code
to implement it at RTL level. Will also coverInverting tristate buffer