Getting through interviews is always a challenging task and requires thorough preparation. Here is a list of probable questions that may appear in an interview related to RTL skills.
RTL or Register Transfer Level Logic Design Questions
Q. How do you differentiate between coding in C/C++ and at RTL (Register Transfer Level) ? Hint: In RTL logic is divided into sequential and combinational logic blocks. Q. How do you differentiate between wires and registers in Verilog ?Hint:Registers are used to store values and wires are used only for connections. D Flip-flops in Digital design generally represents registers. Q. How do you diff between blocking vs. non-blocking statements in Verilog ? Click here Q. Sensitivity lists declaration in always block for sequential and combinational logic? Q. How to implement tri-state logic in verilog? click here Q. Differentiate between tasks and functions in Verilog? Q. How to implement Half-adder and full-adder in RTL? click here Q. When the latches are inferred in RTL ? Hint :click here Q. How to differentiate between ‘==‘ and ‘= = =‘ logic? Hint : ’===’ are not synthesizable & used in simulations. Q. Differentiate between inter-statement and intra statement delays. Hint: Click here Q What are assertions in digital logic design? Q Can you describe Verilog parameters and parameter passing? Hint: click here Q how do you define Events, transaction, propagation delays and concurrence? Q What is constant propagation for logic during synthesis? Direct link
Q. How to generate clocks on FPGA? Hint : Should use Digital Clock Manager’s for clock generations.
Q. Gated clocks in FPGA implementations ? Hint: No gated clocks in FPGA implementations. Click Here for more fpga interview stuff. Q. Which part of the fpga flow you specify the clock frequency for the design? Hint:- Both synthesis and layout. Q. How to constrain clock crossing paths in design? Hint:- False path it. No need to specify timing information for these paths.
Static Timing Analysis Q. Setup time and hold time in digital circuits. ? Hint : Access from here Q. False path in FPGA’s, Critical path, Negative slack, Jitter vs. clock skew . Q. Routing delay, Flop to out delay, Flop to flop delay, Pad to flop delay, Board delay. Q. Knowledge of Synthesis and layout constraints.