Chip Designing for ASIC/ FPGA Design engineers and Students

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Universal NAND Gate.

Derive AND gate from NAND gate.

Derive OR gate from universal NAND gate

Derive XOR gate from universal NAND gate.

Derive AND gate from NAND gate.

Derive OR gate from universal NAND gate

Derive XOR gate from universal NAND gate.

Two variables K-map (truth table and K-map plot).

Three variables K-map (truth table and K-map plot).

Four variables K-map (truth table and K-map plot).

Binary Numbers discussion.

Decimal to Binary conversions.

Binary to Decimal conversions.

Hexadecimal conversions.

Complement’s of binary numbers.

Binary arithmetic and examples.

Binary subtraction and examples.

Signed Magnitude & examples.

BCD(Binary Coded Digital) addition.

Digital Logic Tutorial to continue.

Decimal to Binary conversions.

Binary to Decimal conversions.

Hexadecimal conversions.

Complement’s of binary numbers.

Binary arithmetic and examples.

Binary subtraction and examples.

Signed Magnitude & examples.

BCD(Binary Coded Digital) addition.

Digital Logic Tutorial to continue.

Interview Questions. Main, FPGA, Digital Fundamentals

Introduction to Verilog RTL

Verilog Operators.

Initial Statements in verilog.

Clock and Reset generation.

Blocking vs. Non-blocking Statements.

Conditional Statements & ‘always’ block.

Counter Implementation.

File Operations - $fopen, $fclose, $fdisplay, $fscanf

Read binary or hex format files - $readmemh, $readmemb.

FOR Loop use in verilog code example

Verilog Operators.

Initial Statements in verilog.

Clock and Reset generation.

Blocking vs. Non-

Conditional Statements & ‘always’ block.

Counter Implementation.

File Operations -

Read binary or hex format files -

FOR Loop use in verilog code example

LTE - Long Term Evolution topics here