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FORUM
Computer Organization.
Memory Organization.
Cache Organization.
Interrupt controller.
Digital Logic Gates symbols and truth table.
Universal NAND Gate.
Derive
AND gate from NAND gate
.
Derive
OR gate from universal NAND gate
Derive
XOR gate from universal NAND gate.
Discussion of Boolean Algebra
.
Duality Principle
and
Huntington Postulates
.
Theorems of Boolean Algebra -
discussion
.
Discussion of Boolean Functions.
Boolean Functions using truth tables.
Implementation of Boolean Functions using gates.
Exercise to minimize Boolean Functions.
Representation of Boolean functions in Canonical
and Standard Forms.
Minterms
and
Maxterms
discussion.
Sum of Minterms.
Product of Maxterms or Canonical Forms.
Karnaugh map or K-
map discussion.
Two variables K-
map
(truth table and K-
map plot).
Three variables K-
map
(truth table and K-
map plot).
Four variables K-
map
(truth table and K-
map plot).
Home
Binary Numbers
1s_complement
2s_complement
Binary Subtraction
Binary Sub. Ex's
Sign_magnitude
SignM EX
Gray Coding
BCD coding
Digital gates
NAND NOR & XNOR
Theorems
Boolean Functions
BFunc Examples
Minterm Maxterm
Sum of Minterms
Prdt of Maxterms
2 var K-map
3 var K-map
4 var K-map
5 var K-map
Prime Implicant
PI example
K-map Ex's
KMap minimization
2 var EX
1’s complement discussion
and
2’s complement discussion.
(Examples.)
Binary coding and
Gray coding
. Discussion with
Verilog rtl code example
s
.
BCD coding and step by step addition approach using EXAMPLES
.
Binary Numbers
discussion
.
Decimal to Binary conversions
.
Binary to Decimal
conversions
.
Hexadecimal
conversions.
Complement’s of
binary numbers.
Binary arithmetic and examples.
Binary subtraction and examples.
Signed Magnitude & examples.
BCD(Binary Coded Digital) addition
.
Digital Logic Tutorial to continue.
Five variables K-
map.
Prime Implicant
and
Gate level minimization
examples.
VERILOG HOME
Interview Questions.
Main
,
FPGA
,
Digital Fundamentals
Introduction to Verilog RTL
Verilog Operators.
Initial Statements in verilog.
Clock and Reset generation.
Blocking vs. Non-
blocking Statements.
Conditional Statements & ‘always’ block.
Counter Implementation.
File Operations -
$fopen, $fclose, $fdisplay, $fscanf
Read binary or hex format files -
$readmemh, $readmemb.
FOR Loop use in verilog code example
Function declaration and call.
Testbench structure.
Random number generation.
Shift micro-
operations use in rtl.
Memory -
synchronous RAM implementation.
Verilog generate for memory instances.
Assertions in Verilog Introduction and few examples.
Media Gallery
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Planning
Arithmetic
,
logical
&
shift
micro-
operations
,
LTE -
Long Term Evolution
topics here