Custom Search
Feedback ? Send it to admin@fullchipdesign.com or join me at fullchip@gmail.com
Legal Disclaimer
Chip Designing for ASIC/ FPGA Design engineers and Students
FULLCHIPDESIGN
Digital-
logic Design... Dream for many students… start learning front-
end…
Legal Disclaimer
Topics @
TYH
:-
4G LTE
Tutorial,
GVIM
editor
,
Smart-
Phone
,
Cloud Computing
RTL Design engineers
FORUM
Computer Organization.
Memory Organization.
Cache Organization.
Interrupt controller.
Clock domain crossing
discussion.
Setup time, hold time and
metastability
Asynchronous
FIFO
design
and depth calculation.
Half-
adder discussion with
circuit and truth-
table.
Full-
adder discussion with
circuit and truth table.
4 bit
binary adder circuit
and examples.
Overflow in
Binary Arithmetic scenarios.
Overflow in
signed magnitude
with examples.
Binary
adder-
subtractor circuit
with examples.
Binary multiplier circuit and discussion.
Parity generation and check,error
,
Truth Table
RTL coding guidelines for digital hardware design.
NAND to inverter conversion (two methods).
VHDL RTL discussion (in short) with examples.
Program to implement synchronous flip flop and use
of conditional statements in VHDL
.
Code to generate a
synchronous latch and logic to correct
it in design.
Use of flip-
flops in a shim to register data. Generally this logic is
implemented in FPGA’s to improve timing.
Program to implement
synchronous counter
.
Stack organization
, LIFO, RPN discussion.
RTL -
Register Transfer Level Design.
CMOS Introduction
-
capacitive parasitic
s,
ground bounce
&
crosstalk.
Silicon IC design process.
Clock Crossing
Async FIFO
Half Adder
Full Adder
Binary Adder
Overflow
Overflow Det
Adder-Subtractor
Multiplier
Parity check
RTL guidelines
NAND to INVERTER
VHDL
RTL
Arith Micro-ops
Stack Org
Parallel proc.
Pipeline proc
CMOS Intro
Introduction to Verilog RTL
Verilog Operators.
Initial Statements in verilog.
Clock and Reset generation.
Blocking vs. Non-
blocking Statements.
Conditional Statements & ‘always’ block.
Counter Implementation.
File Operations -
$fopen, $fclose, $fdisplay, $fscanf
Read binary or hex format files -
$readmemh, $readmemb.
FOR Loop use in verilog code example
Function declaration and call.
Testbench structure.
Random number generation.
Shift micro-
operations use in rtl.
Memory -
synchronous RAM implementation.
Verilog generate for memory instances.
Assertions in Verilog Introduction and few examples.
Verilog Tutorial Topics @ fullchipdesign.
Digital Logic fundamentals topics @ fcd
Digital basics
tutorial
Binary number
discussion, 1 and 2
complement
discussion,
Binary arithmetic
,
Signed Magnitude
,
overflow
,
examples
Gray coding
,
Binary coded digital (BCD) coding
,
BCD addition
Digital logic gates
basic
(AND, OR, XOR, NOT) and
derived
(NAND, NOR and XNOR).
Drive XOR from NAND gates
.
Drive XOR from NOR gates
Discussion of
Boolean Algebra
with examples.
Duality Principle
,
Huntington Postulates
,
Theorems of Boolean Algebra
-
discussion with examples,
Boolean Functions
,
Canonical and Standard Forms
,
Minterms
and
Maxterms
Sum of Minterms
,
Product of Maxterms or Canonical Forms
,
Karnaugh map or K-
map discussion
2
,
3
, ,
4
and
5
var’s
Prime Implicant
and
Gate level minimization examples
.
LTE topics @ FCD
What is LTE? Key driving factors behind 4G technology
.
LTE Data rates and comparison with 3G rates.
Difference between air, radio and core network.
.
Seamless mobility
in 4G.
Evolved Packet Core (EPC) system architecture for all IP.
Mobility Management Entity (MME),
Serving System (S) Architecture (A) Evolution (E) Gateway or
Serving Gateway SGW
.
Packet Data Network (PDN)
SAE Gateway
Enhanced Packet Data Gateway (ePDG)
Multiple antenna techniques
-
MIMO
,
Adaptive antenna systems
-
AAS and
Antenna diversity -
AD
Top Tech Topics
@FCD
K-
map -
2,3,4,5 var & Prime Implicant discussion
Verilog -
learn with examples
Interview questions and hints
Universal NAND Gate.
Derive
AND gate from NAND gate
.
Derive
OR gate from universal NAND gate
Derive
XOR gate from universal NAND gate.
Media Gallery
Las Vegas
Grand Canyon
Alcatraz -
the rock
San Francisco
Napa Valley
Los Angeles
17 Mile Drive
Golden Gate Bridge
Blog-
Planning California Trip
Return to
Verilog Tutorial
Interview Questions.
Main
,
FPGA
,
Digital Fundamentals
Resources
Digital design resources
Clock Domain Crossing
rtl
&
testbench
.
Rate change
(asynchronous)
FIFO
design and
fifo depth calculation.
Half-
adder
,
Full-
adder
, 4-
bit
binary adder
,
adder-
subtractor
circuit,
overflow
with
rtl
&
testbench
.
Binary Multiplier
,
Parity error
TT
,
Arithmetic
,
logical
,
shift
micro-
operations
.
Stack organization
,
LIFO, RPN discussion.
RTL coding guidelines
.
ICG
cell,
Assertions
,
levels.
Digital design
Interview
questions.
FPGA
Interview
. FPGA
flow
.
Guide to
Graduate studies in US
Pipeline
vs.
Parallel
processing.
Arithmetic
,
logical
and
shift
microoperations.
Binary to Gray code conversion
Readmemh
,
Readmemb
.
Random
numbers
Memory Implementation
sync Ram and Testbench
Arithmetic
,
logical
,
shift
micro-
operations
,
Overflow