Chip Designing for ASIC/ FPGA Design engineers and Students

FULLCHIPDESIGN

Digital-logic Design...  Dream for many students… start learning front-end…

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Half-adder discussion with circuit and truth-table.

Full-adder discussion with circuit and truth table.

RTL coding guidelines for digital hardware design.

NAND to inverter conversion (two methods).

VHDL RTL discussion (in short) with examples.

Program to implement synchronous flip flop and use of conditional statements in VHDL.

Code to generate a synchronous latch and logic to correct it in design.

Use of flip-flops in a shim to register data. Generally this logic is implemented in FPGA’s to improve timing.

Program to implement synchronous counter in VHDL.

Clock domain crossing discussion with diagram.

Asynchronous FIFO design discussion (step by step approach).