Chip Designing for ASIC/ FPGA Design engineers and Students

FULLCHIPDESIGN

Digital-logic Design... Dream for many students… start learning front-end…

Custom Search

Feedback ? Send it to admin@fullchipdesign.com or join me at fullchip@gmail.com

Binary Multiplier discussion for 2 bits

Lets start the discussion with an example of two bit binary numbers. To explain the carry lets use both numbers as 3.

A = 2‘b11 (In verilog 2‘b stands for 2 bits wide binary number)

B = 2‘b11

A = 2‘b11 (In verilog 2‘b stands for 2 bits wide binary number)

B = 2‘b11

The block diagram implementation of multiplier shows that the circuit requires four AND gates and two half-adders.

Refer half-adders circuit and verilog code from links below

Refer half-

Discussion of Multiplier circuit

Half-Adder , Full-Adder , Adder-Subtractor .

Verilog code - half-adder , full-adder

Verilog code -

Circuit Level Implementation of multiplier is shown below

A0B0

A0

B1

B0

A1

B1

B0

HA

HA

A0B1

A1B0

A1B1

Sum

Carry

Sum

Carry

4’b1001 = 9 in decimal is equivalent to binary multiplication of 2’b11x2’b11.

A

1

1

Multiply B

1

1

Partial Product 1

C 1

C 1

1

1

Partial Product 2

1

1

Sum

1

0

0

1

Binary multiplier is very similar to decimal multiplication. The implementation is discussed in details with diagram and examples.

Resources

Digital design resources

Clock Domain Crossing Discussion with

rtl & testbench example.

Rate change(asynchronous) FIFO design and fifo depth calculation.

Half-adder , Full-adder , 4-bit binary adder , adder-subtractor circuit, overflow with rtl & testbench. Binary Multiplier, Parity error TT

Arithmetic, logical, shift micro-operations . Stack organization, LIFO, RPN discussion.

VHDL rtl - Synchronous flip-flop , latch, shim to improve timing and counter example

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels.

Digital design Interview questions.

FPGA Interview. FPGA flow.

Guide to Graduate studies in US

Pipeline vs. Parallel processing.

Digital design resources

Clock Domain Crossing Discussion with

rtl & testbench example.

Rate change(asynchronous) FIFO design and fifo depth calculation.

Half-

VHDL rtl -

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels.

Digital design Interview questions.

FPGA Interview. FPGA flow.

Guide to Graduate studies in US

Pipeline vs. Parallel processing.