Chip Designing for ASIC/ FPGA Design engineers and Students

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Digital-logic Design...  Dream for many students… start learning front-end…

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Computer Organization.
Memory Organization.
Cache Organization.
Interrupt controller.

Q How are fpga’s different than ASIC’s?
Hint: FPGA’s (Field Programmable Gate Array’s) can easily be re-programmed to a different circuit within few hours. ASIC’s are custom circuits which are manufactured only once (no reuse for different purposes).

Q. Explain CLB’s, LUT’s of FPGA’s ?
Hint: LUT’s, CLB’s or PLB’s. Discussion below

FPGA Look UP Tables (LUT).
LUT is a multi input and single output block that is widely used for logic mapping.

FPGA Interview questions continued.

Q. What are the steps required in building a fpga project?
Hint:- Click here

Q. What information from the targeted fpga device is required in RTL synthesis?
Hint: Device/part number, Speed grade etc.

Device options :-
part number, technology, package, Speed grade etc.

Mapping options:-
resource_sharing 1 (for On)
frequency 10.000 (10 MHz opeartion)
fanout_limit 10000
pipe 1
retiming 1

Many more oprtions are possible and they are dependent on technology.

Q. Which part of the fpga flow you specify the clock frequency for the design?
Hint:- Both synthesis and layout.

Q. How to constrain clock crossing paths in design?
Hint:- False path it. No need to specify timing information for these paths.

Q. How to control resets to designs when the clocks are generated from PLL’s on fpga?
Hint:- Logical ‘AND ‘of external hardware reset and PLL lock signal.

Q. What kind of sanity checks one should do from rtl synthesis

Hint: Look for latches, feedback-muxes, combinational loops, tristate logic, black boxes etc.

Q. What kind of sanity checks one should do from Place and route logs?
Hint:
1. Look at the design utilization.
2. Look for unconnected IO’s.
3. Timing report should not have any failing paths. No setup and hold violations.  

Misc. Verilog RTL examples:-

Binary to Gray Code conversion
File read write operations.
Clock domain crossing.
Half-adder, Full-adder, Tri-state buffer .
Verilog testbench to validate half-adder, full-adder and tri-state buffer.

VERILOG HOME

FPGA PLB’s or CLB’s.
A typical layout of the FPGA is an array of interconnected programmable logic(PLB) blocks or configurable logic blocks (CLB).

A PLB or CLB can be made up of
One or more of LUT’s, one or more of adders and Registers.

Top Tech Topics @FCD

K-map - 2,3,4,5 var & Prime Implicant discussion

Verilog - learn with examples

Interview questions and hints

Media Gallery
Las Vegas
Grand Canyon
Alcatraz -the rock
San Francisco
Napa Valley
Los Angeles
17 Mile Drive
Golden Gate Bridge
Blog- Planning California Trip

Q What are the different fpga flow’s primarily used in industry?
Hint: Altera, Xilinx, Lattice Semiconductor,  etc.

Digital Logic fundamentals topics @ fcd
Digital basics tutorial
Binary number discussion, 1 and 2 complement discussion,
Binary arithmetic, Signed Magnitude, overflow, examples
Gray coding, Binary coded digital (BCD) coding, BCD addition
Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates
Discussion of Boolean Algebra with examples.
Duality Principle, Huntington Postulates, Theorems of Boolean Algebra - discussion with examples, Boolean Functions, Canonical and Standard Forms, Minterms and Maxterms
Sum of Minterms, Product of Maxterms or Canonical Forms,
Karnaugh map or K-map discussion 2, 3, ,4 and 5 var’s

Interview Questions. Main, FPGA, Digital Fundamentals

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