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signal sig_write_data : std_logic;
begin
Process (clk, rst)
begin
if (rst = '0') then
sig_write_data <= '0';
elsif (clk'event and clk = '1') then
sig_write_data <= '1';
else
sig_write_data <= '0';
end if;
end process ;
end
Generation of latches in Digital Design should be avoided by correctly declaring all possible states in conditional statements.
architecture rtl of test is
signal sig_write_data : std_logic;
begin
Process (clk, rst)
begin
if (rst = '0') then
sig_write_data <= '0';
elsif (clk'event and clk = '1') then
sig_write_data <= '1';
end if;
end process ;
end;
This code can be corrected by adding another else statement in the conditional if then else statement
else sig_write_data <= '0';
architecture rtl of test is
VHDL VHSIC (Very High Speed Integrated Circuit) Hardware Description Language.
Following programs are discussed in this section
- Program to implement synchronous flip flop and use of conditional statements in VHDL.
- Code to generate a synchronous latch and logic to correct it in design.
- Use of flip-
flops in a shim to register data. Generally this logic is implemented in FPGA’s to improve timing. - Program to implement synchronous counter in VHDL.