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signal sig_write_data : std_logic;
begin
Process (clk, rst)
begin
if (rst = '0') then
sig_write_data <= '0';
elsif (clk'event and clk = '1') then
sig_write_data <= '1';
else
sig_write_data <= '0';
end if;
end process ;
end
Generation of latches in Digital Design should be avoided by correctly declaring all possible states in conditional statements.
architecture rtl of test is
signal sig_write_data : std_logic;
begin
Process (clk, rst)
begin
if (rst = '0') then
sig_write_data <= '0';
elsif (clk'event and clk = '1') then
sig_write_data <= '1';
end if;
end process ;
end;
This latch code can be corrected or fixed by adding another else statement in the conditional if then else statement
architecture rtl of test is
VHDL VHSIC (Very High Speed Integrated Circuit) Hardware Description Language.
Following programs are discussed in this section
- Program to implement synchronous flip flop and use of conditional statements in VHDL.
- Code to generate a synchronous latch and logic to correct it in design.
- Use of flip-
flops in a shim to register data. Generally this logic is implemented in FPGA’s to improve timing. - Program to implement synchronous counter in VHDL.
Verilog Operators.
Initial Statements in verilog.
Clock and Reset generation.
Blocking vs. Non-
Conditional Statements & ‘always’ block.
Counter Implementation.
File Operations -
Read binary or hex format files -
FOR Loop use in verilog code example
Digital basics tutorial
Binary number discussion, 1 and 2 complement discussion,
Binary arithmetic, Signed Magnitude, overflow, examples
Gray coding, Binary coded digital (BCD) coding, BCD addition
Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates
Discussion of Boolean Algebra with examples.
Duality Principle, Huntington Postulates, Theorems of Boolean Algebra -
Karnaugh map or K-
Prime Implicant and Gate level minimization examples.
Digital design resources
Clock Domain Crossing Discussion with
rtl & testbench example.
Rate change(asynchronous) FIFO design and fifo depth calculation.
Half-
VHDL rtl -
RTL coding guidelines. ICG cell, Assertions, $assertkill, levels.
Digital design Interview questions.
FPGA Interview. FPGA flow.
Guide to Graduate studies in US
Pipeline vs. Parallel processing.