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signal sig_write_data : std_logic;

begin

Process (clk, rst)

begin

if (rst = '0') then

sig_write_data <= '0';

elsif (clk'event and clk = '1') then

sig_write_data <= '1';

else

sig_write_data <= '0';

end if;

end process ;

end

Generation of latches in Digital Design should be avoided by correctly declaring all possible states in conditional statements.

architecture rtl of test is

signal sig_write_data : std_logic;

begin

Process (clk, rst)

begin

if (rst = '0') then

sig_write_data <= '0';

elsif (clk'event and clk = '1') then

sig_write_data <= '1';

end if;

end process ;

end;

This latch code can be corrected or fixed by adding another else statement in the conditional if then else statement

architecture rtl of test is

VHDL VHSIC (Very High Speed Integrated Circuit) Hardware Description Language.

Following programs are discussed in this section

- Program to implement synchronous flip flop and use of conditional statements in VHDL.
- Code to generate a synchronous latch and logic to correct it in design.
- Use of flip-
flops in a shim to register data. Generally this logic is implemented in FPGA’s to improve timing. - Program to implement synchronous counter in VHDL.

Introduction to Verilog RTL

Verilog Operators.

Initial Statements in verilog.

Clock and Reset generation.

Blocking vs. Non-blocking Statements.

Conditional Statements & ‘always’ block.

Counter Implementation.

File Operations - $fopen, $fclose, $fdisplay, $fscanf

Read binary or hex format files - $readmemh, $readmemb.

FOR Loop use in verilog code example

Verilog Operators.

Initial Statements in verilog.

Clock and Reset generation.

Blocking vs. Non-

Conditional Statements & ‘always’ block.

Counter Implementation.

File Operations -

Read binary or hex format files -

FOR Loop use in verilog code example

Digital Logic fundamentals topics @ fcd

Digital basics tutorial

Binary number discussion, 1 and 2 complement discussion,

Binary arithmetic, Signed Magnitude, overflow, examples

Gray coding, Binary coded digital (BCD) coding, BCD addition

Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates

Discussion of Boolean Algebra with examples.

Duality Principle, Huntington Postulates, Theorems of Boolean Algebra - discussion with examples, Boolean Functions, Canonical and Standard Forms, Minterms and Maxterms

Sum of Minterms, Product of Maxterms or Canonical Forms,

Karnaugh map or K-map discussion 2, 3, ,4 and 5 var’s

Prime Implicant and Gate level minimization examples.

Digital basics tutorial

Binary number discussion, 1 and 2 complement discussion,

Binary arithmetic, Signed Magnitude, overflow, examples

Gray coding, Binary coded digital (BCD) coding, BCD addition

Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates

Discussion of Boolean Algebra with examples.

Duality Principle, Huntington Postulates, Theorems of Boolean Algebra -

Karnaugh map or K-

Prime Implicant and Gate level minimization examples.

Resources

Digital design resources

Clock Domain Crossing Discussion with

rtl & testbench example.

Rate change(asynchronous) FIFO design and fifo depth calculation.

Half-adder , Full-adder , 4-bit binary adder , adder-subtractor circuit, overflow with rtl & testbench. Binary Multiplier, Parity error TT

Arithmetic, logical, shift micro-operations . Stack organization, LIFO, RPN discussion.

VHDL rtl - Synchronous flip-flop , latch, shim to improve timing and counter example

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels.

Digital design Interview questions.

FPGA Interview. FPGA flow.

Guide to Graduate studies in US

Pipeline vs. Parallel processing.

Digital design resources

Clock Domain Crossing Discussion with

rtl & testbench example.

Rate change(asynchronous) FIFO design and fifo depth calculation.

Half-

VHDL rtl -

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels.

Digital design Interview questions.

FPGA Interview. FPGA flow.

Guide to Graduate studies in US

Pipeline vs. Parallel processing.