Verilog code for clock domain crossing.
Following block diagram can used to implement clock domain crossing for phase offset clocks
in digital design.
Discussion on clock domain crossing
Verilog RTL code for synchronization
logic to implement clock domain crossing circuit:-
module clk_2_cross ( clock1, clock2, rst_n, data_in, data_out);
input clock1; input clock2; input rst_n; output data_out; input data_in;
reg data_out_meta;
reg [1:0] data_out_reg;
// Assign statements
assign data_out = data_out_reg[1];
// Always block to declare synchronous logic from source clock domain
always @ (posedge clock1)
begin
data_out_meta <= data_in;
end
// Always block to declare synchronous logic in destination clock domain
always @ (posedge clock2 or negedge rst_n)
begin
if (! rst_n)
data_out_reg <= 'b0;
else
// Implement shift register for two flops.
data_out_reg <= {data_out_reg[0], data_out_meta};
end
endmodule
// Note: Above shift register can also be implemented // like below:
// data_out_reg[0] <= data_out_meta;
// data_out_reg[1] <= data_out_reg[0];
Verilog RTL code examples for front-