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Verilog code for clock domain crossing
Verilog code:-
// Module declaration with IO list
module clk_2_cross ( clock1, clock2, rst_n, data_in, data_out);
input clock1;
input clock2;
input rst_n;
output [7:0] data_out;
input [7:0] data_in;
reg [7:0] data_out_meta;
reg [7:0] data_out_reg;
reg [7:0] data_out_reg_r;
wire[7:0] data_out;
// Assign statements
assign data_out = data_out_reg_r;
// Always block to declare synchronous logic from source clock domain
always @ (posedge clock1)
begin
data_out_meta <= data_in;
end
// Always block to declare synchronous logic in destination clock domain
always @ (posedge clock2 or negedge rst_n)
begin
if (! rst_n)
begin
data_out_reg <= 'b0;
data_out_reg_r <= 'b0;
end
else
begin
data_out_reg <= data_out_meta;
data_out_reg_r <= data_out_reg;
end
end
endmodule
Following block diagram can used to implement clock domain crossing for phase offset clocks in digital design.
