Chip Designing for ASIC/ FPGA Design engineers and Students

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Digital-logic Design...  Dream for many students… start learning front-end…

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Computer Organization.
Memory Organization.
Cache Organization.
Interrupt controller.

Step 1 - Synthesis

Synthesize all the RTL source code using one of industry standard tools to create a database of nets, gates, RAM’s, LUT’s (Look Up Table’s - most common for FPGA’s) that layout tools can read.

Step 2 - Layout/Device Pin-map

Write a pin file to map RTL top-level Inputs/Outputs to fpga physical pins. Also set correct drive strengths, voltages for the IO’s.

5 Steps required to build a functional FPGA load (valid for most EDA flows)

Step 3 - Constraints file

Write a constraints file to do define rules for EDA flow :-

Create clocks and set frequencies in terms of periods (1/f).
Define generated clocks, mostly divided clocks from PLL output’s.
Resets and associated constraints (like false path).
Set false path between asynchronous logic.
Define multi-cycle paths etc.




Step 4 - Place and Route

Import synthesized netlist into Place and Route (Layout) tool to do actual floor-plan static timing analysis and gate level layout of synthesized (step 1) netlist.




Step 5 - Static Timing Analysis

The most important step is to analyzed the final netlist against the constraints specified in Step3. In this step we look for setup time violations, hold time violations. The reports with significant timing violations needs to be carefully analyzed and necessary changes needs to be incorporated in designs.  

Resources

Digital design resources
Clock Domain Crossing Discussion with
rtl & testbench example.

Rate change(asynchronous) FIFO design and fifo depth calculation.

Half-adder, Full-adder, 4-bit binary adder , adder-subtractor circuit, overflow with rtl & testbench. Binary Multiplier, Parity error TT
Arithmetic, logical, shift micro-operations. Stack organization, LIFO, RPN discussion.
VHDL rtl - Synchronous flip-flop, latch, shim to improve timing and counter example

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels.
Digital design Interview questions.
FPGA Interview. FPGA flow.
Guide to Graduate studies in US

Pipeline vs. Parallel

Misc. Verilog RTL examples:-

Binary to Gray Code conversion
File read write operations.
Clock domain crossing.
Half-adder, Full-adder, Tri-state buffer .
Verilog testbench to validate half-adder, full-adder and tri-state buffer.

VERILOG HOME

Interview Questions. Main, FPGA, Digital Fundamentals