
Feedback ? Send it to admin@fullchipdesign.com or join me at fullchip@gmail.com
// Full Adder rtl
module full_adder
(in_x, in_y, carry_in, sum_out, carry_out);
input in_x;
input in_y;
input carry_in;
output sum_out;
output carry_out;
wire w_sum1;
wire w_carry1;
wire w_carry2;
assign carry_out = w_carry1 | w_carry2;
half_adder u1_half_adder
(
.in_x(in_x),
.in_y(in_y),
.out_sum(w_sum1),
.out_carry(w_carry1)
);
half_adder u2_half_adder
(
.in_x(w_sum1),
.in_y(carry_in),
.out_sum(sum_out),
.out_carry(w_carry2)
);
endmodule
Checkout test-
Results:
-
1 Bit Full-
-
in_x = 0, in_y = 0, carry_in = 0, out_sum_fa = 0, out_carry_fa = 0
in_x = 0, in_y = 0, carry_in = 1, out_sum_fa = 1, out_carry_fa = 0
in_x = 0, in_y = 1, carry_in = 1, out_sum_fa = 0, out_carry_fa = 1
in_x = 0, in_y = 1, carry_in = 0, out_sum_fa = 1, out_carry_fa = 0
in_x = 0, in_y = 1, carry_in = 1, out_sum_fa = 0, out_carry_fa = 1
in_x = 1, in_y = 1, carry_in = 1, out_sum_fa = 1, out_carry_fa = 1
in_x = 1, in_y = 0, carry_in = 1, out_sum_fa = 0, out_carry_fa = 1
in_x = 1, in_y = 0, carry_in = 0, out_sum_fa = 1, out_carry_fa = 0
in_x = 0, in_y = 1, carry_in = 1, out_sum_fa = 0, out_carry_fa = 1