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Digital Basics Tutorial.
~\Desktop\FCD\temp\temp.v.txt.html // Full Adder rtl

module full_adder
(in_x, in_y, carry_in, sum_out,
carry_out);
 
input  in_x;
input  in_y;
input  carry_in;
output sum_out;
output carry_out;

wire w_sum1;
wire w_carry1;
wire w_carry2;

assign carry_out = w_carry1 | w_carry2;

// Instantiate two half-adders to make the circuit. Click here for half-adder rtl

half_adder u1_half_adder
(
.in_x(in_x),
.in_y(in_y),
.out_sum(w_sum1),
.out_carry(w_carry1)
);                    
half_adder u2_half_adder
(
.in_x(w_sum1),
.in_y(carry_in),
.out_sum(sum_out),
.out_carry(w_carry2)
);              
endmodule

Full-Adder discussion with verilog rtl and testbench
Verilog RTL example for full-adder. Check the half-adder and full-adder discussion in digital design

Checkout verilog test-bench code to validate full-adder design.

Final results from the test-bench are shown below.

in_x = 0, in_y = 0, carry_in = 0, out_sum_fa = 0, out_carry_fa = 0

in_x = 0, in_y = 0, carry_in = 1, out_sum_fa = 1, out_carry_fa = 0

in_x = 0, in_y = 1, carry_in = 1, out_sum_fa = 0, out_carry_fa = 1

in_x = 0, in_y = 1, carry_in = 0, out_sum_fa = 1, out_carry_fa = 0

in_x = 0, in_y = 1, carry_in = 1, out_sum_fa = 0, out_carry_fa = 1

in_x = 1, in_y = 1, carry_in = 1, out_sum_fa = 1, out_carry_fa = 1

in_x = 1, in_y = 0, carry_in = 1, out_sum_fa = 0, out_carry_fa = 1

in_x = 1, in_y = 0, carry_in = 0, out_sum_fa = 1, out_carry_fa = 0

in_x = 0, in_y = 1, carry_in = 1, out_sum_fa = 0, out_carry_fa = 1

Interview Questions. Main, FPGA, Digital Fundamentals
Return to Verilog Tutorial
Half-adder.Tristate buffer.