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Initial stmts.

IF-ELSE.

Case stms.

Readmemh.

Function.

Testbench.

Binary to Gray.

Cllock Crossing.

Half-adder.

Full-adder.

Tristate buffer.

Adder tb.

Counter_enable.

Blocking.

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Full-Adder discussion with verilog rtl and testbench
Verilog RTL example for full-adder. Check the full-adder discussion in digital design section for half-adder circuit and truth table.

// Full Adder rtl

module full_adder

(in_x, in_y, carry_in, sum_out, carry_out);

 

input  in_x;

input  in_y;

input  carry_in;

output sum_out;

output carry_out;

wire w_sum1;

wire w_carry1;

wire w_carry2;

assign carry_out = w_carry1 | w_carry2;

// Click here for half-adder code

half_adder u1_half_adder

(

.in_x(in_x),

.in_y(in_y),

.out_sum(w_sum1),

.out_carry(w_carry1)

);                    

half_adder u2_half_adder

(

.in_x(w_sum1),

.in_y(carry_in),

.out_sum(sum_out),

.out_carry(w_carry2)

);               

endmodule

Checkout test-bench here

Results:

---------------------

1 Bit Full-Adder

----------------------

in_x = 0, in_y = 0, carry_in = 0, out_sum_fa = 0, out_carry_fa = 0

in_x = 0, in_y = 0, carry_in = 1, out_sum_fa = 1, out_carry_fa = 0

in_x = 0, in_y = 1, carry_in = 1, out_sum_fa = 0, out_carry_fa = 1

in_x = 0, in_y = 1, carry_in = 0, out_sum_fa = 1, out_carry_fa = 0

in_x = 0, in_y = 1, carry_in = 1, out_sum_fa = 0, out_carry_fa = 1

in_x = 1, in_y = 1, carry_in = 1, out_sum_fa = 1, out_carry_fa = 1

in_x = 1, in_y = 0, carry_in = 1, out_sum_fa = 0, out_carry_fa = 1

in_x = 1, in_y = 0, carry_in = 0, out_sum_fa = 1, out_carry_fa = 0

in_x = 0, in_y = 1, carry_in = 1, out_sum_fa = 0, out_carry_fa = 1

Full - adder test-bench