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module full_adder
(in_x, in_y, carry_in, sum_out,
carry_out);
input in_x;
input in_y;
input carry_in;
output sum_out;
output carry_out;
wire w_sum1;
wire w_carry1;
wire w_carry2;
assign carry_out = w_carry1 | w_carry2;
// Instantiate two half-adders to make the circuit. Click here for half-adder rtl
half_adder u1_half_adder
(
.in_x(in_x),
.in_y(in_y),
.out_sum(w_sum1),
.out_carry(w_carry1)
);
half_adder u2_half_adder
(
.in_x(w_sum1),
.in_y(carry_in),
.out_sum(sum_out),
.out_carry(w_carry2)
);
endmodule
Full-Adder discussion with verilog rtl and testbench
Verilog RTL example for full-adder. Check the half-adder and full-adder discussion in digital design
Checkout verilog test-
Final results from the test-
in_x = 0, in_y = 0, carry_in = 0, out_sum_fa = 0, out_carry_fa = 0
in_x = 0, in_y = 0, carry_in = 1, out_sum_fa = 1, out_carry_fa = 0
in_x = 0, in_y = 1, carry_in = 1, out_sum_fa = 0, out_carry_fa = 1
in_x = 0, in_y = 1, carry_in = 0, out_sum_fa = 1, out_carry_fa = 0
in_x = 0, in_y = 1, carry_in = 1, out_sum_fa = 0, out_carry_fa = 1
in_x = 1, in_y = 1, carry_in = 1, out_sum_fa = 1, out_carry_fa = 1
in_x = 1, in_y = 0, carry_in = 1, out_sum_fa = 0, out_carry_fa = 1
in_x = 1, in_y = 0, carry_in = 0, out_sum_fa = 1, out_carry_fa = 0
in_x = 0, in_y = 1, carry_in = 1, out_sum_fa = 0, out_carry_fa = 1
Full - adder test-bench Half-Adder , Full-Adder , Adder-Subtractor . Verilog code - Half-Adder , Full-Adder
Resources
Digital design resources
Clock Domain Crossing Discussion with
rtl & testbench example.
Rate change(asynchronous) FIFO design and fifo depth calculation.
Half-adder , Full-adder , 4-bit binary adder , adder-subtractor circuit, overflow with rtl & testbench. Binary Multiplier, Parity error TT
Arithmetic, logical, shift micro-operations . Stack organization, LIFO, RPN discussion.
VHDL rtl - Synchronous flip-flop , latch, shim to improve timing and counter example
RTL coding guidelines. ICG cell, Assertions, $assertkill, levels.
Digital design Interview questions.
FPGA Interview. FPGA flow.
Guide to Graduate studies in US
Pipeline vs. Parallel processing.
Digital design resources
Clock Domain Crossing Discussion with
rtl & testbench example.
Rate change(asynchronous) FIFO design and fifo depth calculation.
Half-
VHDL rtl -
Digital design Interview questions.
FPGA Interview. FPGA flow.
Guide to Graduate studies in US
Pipeline vs. Parallel processing.
Interview Questions. Main, FPGA, Digital Fundamentals
Arithmetic, logical and shift microoperations.
Binary to Gray code conversion
Readmemh, Readmemb. Random numbers
Memory Implementation - sync Ram and Testbench
Binary to Gray code conversion
Readmemh, Readmemb. Random numbers
Memory Implementation -
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