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Computer Organization.
Memory Organization.
Cache Organization.
Interrupt controller.

When we declare $assertkill or $assertoff or $asserton all the levels of hierarchy is included by default.

In order specify limited modules or levels in the design we can employ following extra controls in the declaration.



Concise control assertions are listed below with hierarchical controls.

$assertkill (commen1below [, commen2below, ...]);
$assertoff (commen1below [, commen2below, ...]);
$asserton (commen1below [, commen2below, ...]);



Commen1below : -  This can be either 1 or 0
1 = Only specified module, in the hierarchy.
 0 = current module and all modules below  in the       hierarchy.

Comment2below  :-  In this area either module names or  assertion names can be specified.

On this page - Concise assertions with hierarchy. Next blog - Chandle for “DPI-C”

Misc. Verilog RTL examples:-

Binary to Gray Code conversion
File read write operations.
Clock domain crossing.
Half-adder, Full-adder, Tri-state buffer .
Verilog testbench to validate half-adder, full-adder and tri-state buffer.

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