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Check out Verilog code for clock domain crossing
Verilog testbench Example
Test Bench to generate 8 bit packets, Example to show a counter code and case statement usage
module tb_c2cross
( );
reg clk_1fs, clk_1fs_d;
reg rst_n;
reg writep;
reg [7:0] r_count, count, r_packet_in, packet_in;
reg wr_en, r_wr_en, rd_en, r_rd_en;
reg [1:0] r_rd_count,rd_count;
// Use of initial statement to generate clocks 1fs and 1fs_d
initial begin
clk_1fs = 0; clk_1fs_d = 0; rst_n = 0; #100 rst_n = 1;
forever begin
#10 clk_1fs = 1; #11 clk_1fs_d = 1; #10 clk_1fs = 0; #11 clk_1fs_d = 0; end end
// Always block to generate synchronous packets in 1fs clock domain
always@(posedge clk_1fs or negedge rst_n)
begin
if (!rst_n) begin
r_packet_in <= 'b0; r_count <= 'b0; r_rd_count <= 'b0; r_wr_en <= 'b0; r_rd_en <= 'b0; end
else begin
r_packet_in <= packet_in; r_count <= count + 1 ; r_rd_count <= rd_count + 1 ;
r_wr_en <= wr_en; r_rd_en <= rd_en; end end
// Combinational logic to implement case statement to generate packets
always@(*)
begin
packet_in = 'h0; count = r_count; wr_en = r_wr_en;
rd_count = r_rd_count;
rd_en = r_rd_en;
if (r_rd_count == 'd3) rd_en = 'd1;
else rd_en = 'd0;
case (r_count)
10 : begin
packet_in = 'haa; wr_en = 'b1; end
11 : begin
packet_in = 'hbb; wr_en = 'b1; end
12 : begin
packet_in = 'hcc; wr_en = 'b1; end
13 : begin
packet_in = 'hdd; wr_en = 'b1; end
14 : begin
packet_in = 'hee; wr_en = 'b1; end
15 : begin
packet_in = 'hff; wr_en = 'b1; end
default: begin
packet_in = 'd0; wr_en = 'd0; end
endcase end
// Instance for clock domain crossing
clk_2_cross u_clock_2_cross
(
.clk_1fs(clk_1fs), .clk_1fs_d(clk_1fs_d), .rst_n(rst_n), .data_in(r_packet_in), .data_out() );
endmodule
