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Advanced SV simulators support concise assertion techniques/approaches.

In order to implement the techniques follow the steps listed below:-

Step 1. Default clocking blocks (DCB) - The default clocking block can be used to unify the definition of ‘posedge’ to sample the digital signals. In designs with DCB the concurrent assertions can easliy inherit the sampling properties (like positive edge of sampling clock).

Example:
default clocking dcb @(posedge clk);
endclocking  
Step 2. Implement ‘always’ block to disable all assertions with ‘not of reset’ else enable back.

Example:-
Always @(reset)
if (~reset) $assertkill;
else         $asserton;

Alternate approach to 1 and 2. Most simulators doesn’t support concise assertions techniques. For these simulators the engineer can implement smart macros.
SystemVerilog (SV) assertions - $assertkill or $assertoff or $asserton
When or How to use $assertkill or $assertoff or $asserton

Definition of three concise assertions:-
$assertoff - used to disable all assertions but allows currently active assertions to
complete before being disabled.
$assertkill - used to kill and disable all assertions including currently active assertions.
$asserton - used to turn all assertions back on

The above three assertion techniques are also popular with name of concise assertion tricks.
Designers employ them to control the enabling and disabling of all assertions in design.  

Detailed discussion is covered next.
Interview Questions. Main, FPGA, Digital Fundamentals