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Full-Adder discussion

Full-adder is a digital circuit to perform arithmetic sum of two bits and a previous carry. It is represented in the diagram and truth table below.

Click here for Verilog RTL example and test-bench for full-adder.

In_x

In_y

Carry_in

sum_out

Carry_out

0

0

0

0

0

0

0

1

1

0

0

1

0

1

0

0

1

1

0

1

1

0

0

1

0

1

0

1

0

1

1

1

0

0

1

1

1

1

1

1

4 - bit Binary Adder implementation, block diagram and discussion.

4 - bit Binary Adder - Subtractor implementation, block diagram and discussion.

Full Adder Truth table (FA) below:

Carry_out

Half-Adder , Adder-Subtractor .

Verilog code - half-adder , full-adder

Verilog code -

Block Diagram of Full Adder

The circuit involves two half-adders & one OR gate. Alternately 2 XOR gates, 2 AND gates and 1 OR gate. Circuit of full-adder is discussed below:

Interview Questions. Main, FPGA, Digital Fundamentals

Resources

Verilog RTL code examples for front-end chip design.

Digital Design Topics

Half-adder , full-adder ,

Adder-sub tractor

Stack Organization - LIFO, RPN

Parity Generation and error checking

Binary multiplier circuit.

CMOS introduction

Digital fundamentals -

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels. Chandle

Pipeline vs. Parallel processing.

Verilog RTL code examples for front-

Half-

Adder-

Stack Organization -

Binary multiplier circuit.

CMOS introduction

Digital fundamentals -

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels. Chandle

Pipeline vs. Parallel processing.

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