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Chip Designing for ASIC/ FPGA Design engineers and Students

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Introduction:-

Binary addition or subtraction can be implemented using a single circuit as discussed below. With this implementation any length (no of bits = N) of binary numbers can be used to calculate the results by using N number of full-adders and N number of XOR gates.

Circuit is very similar to binary adder circuit except of a XOR gate at second input to full-adders.

Circuit is very similar to binary adder circuit except of a XOR gate at second input to full-

Switch Mode (SM) is a control input to the circuit to switch between addition or subtraction operations.

Adder

When SM = 0 the circuit is equivalent to Binary Adder.

B (bit ) XOR 0 = B (bit)

Subtractor

When SM = 1 the circuit is equivalent to Binary subtractor.

B (bit ) XOR 1 = invert(B (bit))

‘B’ input become’s and inverted in this case.

Examples

Refer following sections @ fullchipdesign for examples:-

Binary adder example.

Subtraction examples - Unsigned numbers.

Subtraction examples - Signed numbers.

Adder

When SM = 0 the circuit is equivalent to Binary Adder.

B (bit ) XOR 0 = B (bit)

Subtractor

When SM = 1 the circuit is equivalent to Binary subtractor.

B (bit ) XOR 1 = invert(B (bit))

‘B’ input become’s and inverted in this case.

Examples

Refer following sections @ fullchipdesign for examples:-

Subtraction examples -

Full-Adder

Full-Adder

Full-Adder

Full-Adder

A0

A3

A2

A1

S3

S2

S1

S0

C2

C3

C0

C1

C4

Switch Mode

(SM)

(SM)

Discussion of Adder-Subtractor circuit

Half-Adder , Full-Adder , Adder-Subtractor . Verilog code - half-adder , full-adder

Interview Questions. Main, FPGA, Digital Fundamentals

Circuit Level Implementation