Chip Designing for ASIC/ FPGA Design engineers and Students
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Parity Output
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Parity Generation Truth Table
Parity Check Truth Table
Resources
Digital design resources
Clock Domain Crossing rtl & testbench.
Rate change (asynchronous) FIFO design and fifo depth calculation.
Half-adder , Full-adder , 4-bit binary adder , adder-subtractor circuit, overflow with rtl & testbench.
Binary Multiplier, Parity error TT,
Arithmetic, logical, shift micro-operations .
Stack organization, LIFO, RPN discussion.
RTL coding guidelines. ICG cell,
Assertions, $assertkill, levels.
Digital design Interview questions.
FPGA Interview. FPGA flow.
Guide to Graduate studies in US
Pipeline vs. Parallel processing.
Digital design resources
Clock Domain Crossing rtl & testbench.
Rate change (asynchronous) FIFO design and fifo depth calculation.
Half-
Binary Multiplier, Parity error TT,
Arithmetic, logical, shift micro-
Stack organization, LIFO, RPN discussion.
RTL coding guidelines. ICG cell,
Assertions, $assertkill, levels.
Digital design Interview questions.
FPGA Interview. FPGA flow.
Guide to Graduate studies in US
Pipeline vs. Parallel processing.
Introduction to Verilog RTL
Verilog Operators.
Initial Statements in verilog.
Clock and Reset generation.
Blocking vs. Non-blocking Statements.
Conditional Statements & ‘always’ block.
Counter Implementation.
File Operations - $fopen, $fclose, $fdisplay, $fscanf
Read binary or hex format files - $readmemh, $readmemb.
FOR Loop use in verilog code example
Verilog Operators.
Initial Statements in verilog.
Clock and Reset generation.
Blocking vs. Non-
Conditional Statements & ‘always’ block.
Counter Implementation.
File Operations -
Read binary or hex format files -
FOR Loop use in verilog code example
Cloud Computing ?
Whenever a document or photo is uploaded on the web, a thread of cloud computing is active. Learn more from here.
Whenever a document or photo is uploaded on the web, a thread of cloud computing is active. Learn more from here.
Digital Logic fundamentals topics @ fcd
Digital basics tutorial
Binary number discussion, 1 and 2 complement discussion,
Binary arithmetic, Signed Magnitude, overflow, examples
Gray coding, Binary coded digital (BCD) coding, BCD addition
Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates
Discussion of Boolean Algebra with examples.
Duality Principle, Huntington Postulates, Theorems of Boolean Algebra - discussion with examples, Boolean Functions, Canonical and Standard Forms, Minterms and Maxterms
Sum of Minterms, Product of Maxterms or Canonical Forms,
Karnaugh map or K-map discussion 2, 3, ,4 and 5 var’s
Digital basics tutorial
Binary number discussion, 1 and 2 complement discussion,
Binary arithmetic, Signed Magnitude, overflow, examples
Gray coding, Binary coded digital (BCD) coding, BCD addition
Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates
Discussion of Boolean Algebra with examples.
Duality Principle, Huntington Postulates, Theorems of Boolean Algebra -
Karnaugh map or K-
Evolved Packet Core (EPC) system architecture for all IP.Mobility Management Entity (MME),
Serving System (S) Architecture (A) Evolution (E) Gateway or Serving Gateway SGW. Packet Data Network (PDN) SAE Gateway. Enhanced Packet Data Gateway (ePDG)
Multiple antenna techniques -
Serving System (S) Architecture (A) Evolution (E) Gateway or Serving Gateway SGW. Packet Data Network (PDN) SAE Gateway. Enhanced Packet Data Gateway (ePDG)
Multiple antenna techniques -
PRE stands for Parity Receive Error check.
Interview Questions. Main, FPGA, Digital Fundamentals