RTL Coding guidelines
for ASIC/FPGA implementations.
Guideline 1:-
Example
if (condition True)
d_ff <= ’b1;
else
d_ff <= ‘b0;
Guideline 2:-
Guideline 3:-
guidelines
for ASIC/FPGA implementations.Guideline 1:-
Example
if (condition True)
d_ff <= ’b1;
else
d_ff <= ‘b0;
Guideline 2:-
Guideline 3:-
Diagram to show routing
of data across FPGA’s and requirements
for doing Static Timing Analysis
Guideline 4:-
Following are some ideas to implement clock domain crossing: Use rate – change FIFO, Double clocking, Gray encoders for counters.
Guideline 5:-
Guideline 6: Blocking vs. non-
Blocking statements are always used within combinatory block to execute statements in a sequence. Non – blocking statements are always executed in a sequential logic block to execute all statements in at either clock edge.
Guideline 7: Never mix blocking and non-
Guideline 8:-
Guideline 9:-
Guideline 10: -
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