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Pipeline Processing :- This technique is most followed technique in the digital design which involves breaking down of an sequential process into sub operations (lets call it sub-blocks). The sub-blocks are then pushed into a series of hardware blocks to process it independent of the complete operation.

Lets first discuss it with virtual pipe block diagram.

Lets first discuss it with virtual pipe block diagram.

An example of non-pipeline vs. pipeline.

4 similar segments/threads needs to be processed through a pipeline design.

Before we implement the design, lets break each segment into 5 sub-blocks that can be processed independent of other blocks. Each sub-block is implemented as a stage in diagram.

Now we can implement the design in following manner. Start pushing each segment through the pipe so that at

Time 1 - Stage 1 is processing - Segment 1, sub-block 1.

Time 2 - Stage 1 is processing - Segment 2, sub-block 1. AND stage 2 is processing - Segment 1, sub-block 2. ... And so-on

Checkout the complete pipeline operation and space time table.

Before we implement the design, lets break each segment into 5 sub-

Now we can implement the design in following manner. Start pushing each segment through the pipe so that at

Time 1 -

Checkout the complete pipeline operation and space time table.

So with pipeline we can implement hardware efficiently.

To calculate speed up in execution time follow following formula:-

Non - pipelined

Time to process 1 segment = t

No of segments = n

Time Without pipeline = nt

Pipelined

Time to process 1 segment = t

No of segments = n

Number of sub-blocks for each segment = k

Time to process each sub-block = t/n

Time With pipeline = (n+k-1)t/n

In our example:- n = 4, t = 5, k = 5

Non- Pipeline = 4*5 = 20

To calculate speed up in execution time follow following formula:-

Non -

No of segments = n

Time Without pipeline = nt

Pipelined

Time to process 1 segment = t

No of segments = n

Number of sub-

Time to process each sub-

In our example:-

Time ->

1

2

3

4

5

6

7

8

Segment 1

T1

T2

T3

T4

T5

Segment 2

T1

T2

T3

T4

T5

Segment 3

T1

T2

T3

T4

T5

Segment 4

T1

T2

T3

T4

T5

Resources

Digital design resources

Clock Domain Crossing Discussion with

rtl & testbench example.

Rate change(asynchronous) FIFO design and fifo depth calculation.

Half-adder , Full-adder , 4-bit binary adder , adder-subtractor circuit, overflow with rtl & testbench. Binary Multiplier, Parity error TT

Arithmetic, logical, shift micro-operations . Stack organization, LIFO, RPN discussion.

VHDL rtl - Synchronous flip-flop , latch, shim to improve timing and counter example

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels.

Digital design Interview questions.

FPGA Interview. FPGA flow.

Digital design resources

Clock Domain Crossing Discussion with

rtl & testbench example.

Rate change(asynchronous) FIFO design and fifo depth calculation.

Half-

VHDL rtl -

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels.

Digital design Interview questions.

FPGA Interview. FPGA flow.

Interview Questions. Main, FPGA, Digital Fundamentals