Chip Designing for ASIC/ FPGA Design engineers and Students

FULLCHIPDESIGN

Digital-logic Design...  Dream for many students… start learning front-end…

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PICS

Computer Organization.
Memory Organization.
Cache Organization.
Interrupt controller.

Events, transaction, propagation delays and concurrence

Lets start our discussion with an example of half-adder circuit. Half-adder circuit shown below has 3 inputs (x, y and carry_in) and 2 outputs (sum and carry_out). This circuit computes sum of two bits and reports carry.

Event - Whenever there is a change at input there is a corresponding change at the output. This change is know as an “event” in digital circuit design and analysis.

Transaction - Its not necessary that a change at input will result in an output change. This scenario is know as transaction.

Before we go any forward, lets discuss more about physical layout of digital circuits. -
The physical design primarily consists of devices like transistors, wire and noise canceling circuits. The transistors can itself be laid out in various structures to create logic gates , flip-flops etc.

Propagation Delay - Whenever a change is applied at the input of a circuit there is an associated delay or resistance in the path. This period of time is known as Propagation delay. These delays are also know as inertial delays and their values are directly proportional to the length of wire.

Concurrent Operations in digital circuits:
Whenever two different signals change values due to change in any one or more inputs are a result of concurrency in digital circuit. In our example change in any one input can result in a different value at the output. Refer Truth-table below.

Truth table for Half-adder circuit is shown below:

From the truth-table enclosed in dotted box above:

Event: Input_y transitioning from 0 to 1.

Concurrent operation results:
Output_sum going from 1 to 0
Output_carry going from 0 to 1.

Effect of Propagation Delay:
The outputs Sum and Carry may not change simultaneously due to propagation delay.  

Introduction to Verilog RTL
Verilog Operators.
Initial Statements in verilog.
Clock and Reset generation.
Blocking vs. Non-blocking Statements.
Conditional Statements & ‘always’ block.
Counter Implementation.
File Operations - $fopen, $fclose, $fdisplay, $fscanf
Read binary or hex format files - $readmemh, $readmemb.
FOR Loop use in verilog code example

Function declaration and call.
Testbench structure.
Random number generation.
Shift micro-operations use in rtl.
Memory - synchronous RAM implementation.
Verilog generate for memory instances.
Assertions in Verilog Introduction and few examples.

Digital Logic fundamentals topics @ fcd
Digital basics tutorial
Binary number discussion, 1 and 2 complement discussion,
Binary arithmetic, Signed Magnitude, overflow, examples
Gray coding, Binary coded digital (BCD) coding, BCD addition
Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates
Discussion of Boolean Algebra with examples.
Duality Principle, Huntington Postulates, Theorems of Boolean Algebra - discussion with examples, Boolean Functions, Canonical and Standard Forms, Minterms and Maxterms
Sum of Minterms, Product of Maxterms or Canonical Forms,
Karnaugh map or K-map discussion 2, 3, ,4 and 5 var’s
Prime Implicant and Gate level minimization examples.

Interview Questions. Main, FPGA, Digital Fundamentals

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Golden Gate Bridge
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Arithmetic, logical and shift microoperations.

Binary to Gray code conversion

Readmemh, Readmemb. Random numbers

Memory Implementation - sync Ram and Testbench

K-map - 2,3,4,5 var & Prime Implicant discussion

Arithmetic, logical, shift micro-operations, Overflow

LTE - Long Term Evolution topics from

Binary adder-subtractor circuit

Full-adder RTL

Binary adder-subtractor circuit