System Verilog alias
statement
Alias is system verilog coding technique to model bi- directional mapping for ‘inout’ ports or wires in a module. In particular, alias mapping is direct connection of one inout port to other. In other way, its a short- circuit of wires. Example below:
module tomap
(inout [2:0] A, B;);
// alias 1
alias B = {A[0], A[1], A[2]};
endmodule
Each signal used in alias statement needs to be same net type. A wire, inout etc.
Each signal used in alias must be of same width.