Chip Designing for ASIC/ FPGA Design engineers and Students
Digital-logic Design... Dream for many students… start learning front-end…
Feedback ? Send it to admin@fullchipdesign.com or join me at fullchip@gmail.com
Introduction
Operators
Initial stms
Block vs. Non Blk
IF-ELSE, CASE
FORLOOP
File Operations
Read .bin format
Function Call
Testbench
Random Numbers
Shift Micro-ops
Sync RAM
Mem Generate
Assertions
// Always block to generate synchronous packets in 1fs clock domain
// Implementing counters
always@(posedge clk_1fs or negedge rst_n)
begin
if (!rst_n) begin
r_packet_in <= 'b0;
r_count <= 'b0;
r_rd_count <= 'b0;
r_wr_en <= 'b0;
r_rd_en <= 'b0;
end
else begin
r_packet_in <= packet_in;
r_count <= count + 1 ;
r_rd_count <= rd_count + 1 ;
r_wr_en <= wr_en;
r_rd_en <= rd_en;
end end
So At negative edge of reset. The events will update concurrently R1,R2,R3,R4,R5
Otherwise,
At positive edge of clock. The events will update concurrently C1,C2,C3,C4,C5
Non-Blocking statements are declared using ‘<=’ operator. For these statements the registers are updated concurrently at the rising edge of the clock or at reset.
Example - Case statements are used in RTL design to model states in Finite State
Machine and for generating conditional statements based on value of a particular
register. Case statement implementation is shown on left.
Example - Counters are extensively used in synchronous RTL. In current implementation, its used for keeping track of packets.
case (r_count)
10 : begin
packet_in = 'haa;
wr_en = 'b1;
end
11 : begin
packet_in = 'hbb;
wr_en = 'b1;
end
12 : begin
packet_in = 'hcc;
wr_en = 'b1;
end
13 : begin
packet_in = 'hdd;
wr_en= 'b1;
end
endcase
Blocking statements are declared using ‘=’ operator. For these statements the registers are updated only when the previous assignment is updated. All the events in this case statements happens only in one sequence.
Verilog Blocking statements
Verilog Blocking & Non-blocking statements
