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Conditional Case Statements
Case statements are used in RTL design to model states in Finite State Machine and for generating conditional statements based on value of a particular register. Case statement implementation is shown below.
case (r_count)
10 : begin
packet_in = 'haa;
wr_en = 'b1;
end
11 : begin
packet_in = 'hbb;
wr_en = 'b1;
end
12 : begin
packet_in = 'hcc;
wr_en = 'b1;
end
13 : begin
packet_in = 'hdd;
wr_en = 'b1;
end
endcase
Check the complete usage of the counter code in the test bench example.
// Always block to generate synchronous packets in 1fs clock domain
// Implementing counters
always@(posedge clk_1fs or negedge rst_n)
begin
if (!rst_n) begin
r_packet_in <= 'b0;
r_count <= 'b0;
r_rd_count <= 'b0;
r_wr_en <= 'b0;
r_rd_en <= 'b0;
end
else begin
r_packet_in <= packet_in;
r_count <= count + 1 ;
r_rd_count <= rd_count + 1 ;
r_wr_en <= wr_en;
r_rd_en <= rd_en;
end
end
