Logical Shift micro-operations RTL

In this section we will implement verilog code for shift micro-operations.

Logical Shift Right (LSR) verilog code and simulation results. LSR discussion here.

Logical Shift left (LSL) verilog code, simulation results.

Circular Shift Right (CSR) verilog code, results and discussion.

Circular Shift Left (CSL) verilog code, simulation results.

Related Topics: Arithmetic, logical, shift micro-operations, Overflow

Verilog code for logical shift right (LSR) microoperations.

LSR RTL.

~\Documents\fullchip\python\mysite\webpages\templates\webpages\test.v.html

// Test Bench for generating random numbers
module shift_tb ();
reg clk, rst;
reg[7:0] x_q;
reg[7:0] x_d;
reg[4:0] q_cnt;

integer k, i;
integer out;
// Generate Clock
initial
begin
    clk = 0;
   forever #10 clk = ~clk;
end
// Release reset
initial begin
    rst = 0;
    # 50 rst = 1;
end
// Use positive edge of clock to shift the register value
// Implement logical right shift
always @(posedge clk or
    negedge rst)
begin
    if (!rst)
    begin
        x_q <= 'hed;
        q_cnt <= 0;
        out = $fopen("shift_LR.vec","w");
    end
    else
    begin
        x_q <= x_d;
        q_cnt <= q_cnt + 1;
        $fdisplay(out, "Pass %d Shift value in hex %b", q_cnt, x_q);
    end
end
// shift logic
always @(*)
begin
    x_d = x_q;
    x_d[7] = 0;
    for (i=0; i<7; i=i+1)
    begin
        x_d[i] = x_q[i+1];
    end
end
endmodule

LSR Results.

LSR shift results

Pass 0 Shift value in hex 11101101
Pass 1 Shift value in hex 01110110
Pass 2 Shift value in hex 00111011
Pass 3 Shift value in hex 00011101
Pass 4 Shift value in hex 00001110
Pass 5 Shift value in hex 00000111
Pass 6 Shift value in hex 00000011
Pass 7 Shift value in hex 00000001
Pass 8 Shift value in hex 00000000 <-- After shift 0 is filled in