Chip Designing for ASIC/ FPGA Design engineers and Students

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Computer Organization.
Memory Organization.
Cache Organization.
Interrupt controller.

Pass  0 Shift value in hex  11101101
Pass  1 Shift value in hex  11011011
Pass  2 Shift value in hex  10110111
Pass  3 Shift value in hex  01101111
Pass  4 Shift value in hex  11011110
Pass  5 Shift value in hex  10111101
Pass  6 Shift value in hex  01111011
Pass  7 Shift value in hex  11110110
Pass  8 Shift value in hex  11101101 <-- Original binary value
Pass  9 Shift value in hex  11011011
Pass 10 Shift value in hex 10110111
Pass 11 Shift value in hex 01101111
Pass 12 Shift value in hex 11011110
Pass 13 Shift value in hex 10111101
Pass 14 Shift value in hex 01111011
Pass 15 Shift value in hex 11110110
Pass 16 Shift value in hex 11101101 <-- Original binary value
Pass 17 Shift value in hex 11011011
Pass 18 Shift value in hex 10110111
Pass 19 Shift value in hex 01101111

Introduction to Verilog RTL
Verilog Operators.
Initial Statements in verilog.
Clock and Reset generation.
Blocking vs. Non-blocking Statements.
Conditional Statements & ‘always’ block.
Counter Implementation.
File Operations - $fopen, $fclose, $fdisplay, $fscanf
Read binary or hex format files - $readmemh, $readmemb.
FOR Loop use in verilog code example

Function declaration and call.
Testbench structure.
Random number generation.
Shift micro-operations use in rtl.
Memory - synchronous RAM implementation.
Verilog generate for memory instances.
Assertions in Verilog Introduction and few examples.

Misc. Verilog RTL examples:-
Binary to Gray Code conversion
File read write operations.
Clock domain crossing.
Half-adder, Full-adder, Tri-state buffer .
Verilog testbench to validate half-adder, full-adder and tri-state buffer.
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Resources

Verilog RTL code examples for front-end chip design.
Digital Design Topics
Half-adder, full-adder,
Adder-sub tractor
Stack Organization - LIFO, RPN
Parity Generation and error checking
Binary multiplier circuit.
CMOS introduction
Digital fundamentals -
RTL coding guidelines. ICG cell, Assertions, $assertkill, levels. Chandle
Pipeline vs. Parallel processing.