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Computer Organization.
Memory Organization.
Cache Organization.
Interrupt controller.

SystemVerilog ‘chandle’ for “DPI-C”

In systemVerilog, ‘chandle’ is used to pass C pointers as arguments to DPI functions or tasks.

Few things to learn about using ‘chandle’

While importing functions as DPI, the ports can’t be declared as chandle data type.

No senstivity list declarations.
chandle can be passed as arguments to functions and tasks. It can also be used within SystemVerilog ‘class’.

Only available for SystemVerilog.

Misc. Verilog RTL examples:-

Binary to Gray Code conversion, File read write operations.
Clock domain crossing, Half-adder, Full-adder, Tri-state buffer, Verilog testbench to validate half-adder, full-adder and tri-state buffer.

VERILOG HOME   Verilog Tutorial

Resources

Clock Domain Crossing Discussion with
rtl & testbench example.

Rate change(asynchronous) FIFO design and fifo depth calculation.

Half-adder, Full-adder, 4-bit binary adder , adder-subtractor circuit, overflow with rtl & testbench. Binary Multiplier, Parity error TT
Arithmetic, logical, shift micro-operations. Stack organization, LIFO, RPN discussion.
VHDL rtl - Synchronous flip-flop, latch, shim to improve timing and counter example

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels.
Digital design Interview questions.
FPGA Interview. FPGA flow.
Guide to Graduate studies in US

Pipeline vs. Parallel processing.

Interview Questions. Main, FPGA, Digital Fundamentals

Example Use: import “DPI-C” function void calc_pass (chandle pointer);

K-map - 2,3,4,5 var & Prime Implicant

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