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ICG cell Assertions Concise assert Assert levels Chandle defparam Parameters Parameters Pass Defparam stms Localparam Constant Pass Alias Array Functions always
Verilog Tutorial.
Digital Basics Tutorial.
Verilog Parameters
What are parameters?
The verilog parameters is a way of passing the constants to modules to overwrite there local constants for signal widths and depths (for memories).  This is done when the block is instantiated in top-level/higher-level module. Parameters also allows easy modifications of the code by changing the
Code snippet from the verilog sync ram page is below:
module mem_ram_sync(

parameter WIDTH=8;
Parameter DEPTH=64;
Parameter LOG2D=6;

input             clk;
input             rst;
input             read_rq;
input             write_rq;
input    [LOG2D -1 :0]  rw_address;
input    [WIDTH - 1 :0]         write_data;
Output [WIDTH - 1:0]          read_data;

reg[7:0]     read_data;
integer out, i;

// Declare memory 64x8 bits = 512 bits or 64 bytes
/* Width of memory 8 bits and Depth of memory 64 locations */
reg [WIDTH-1:0] memory_ram_d [DEPTH-1:0];
reg [WIDTH-1:0] memory_ram_q [DEPTH-1:0];
// Code from here refer sync ram page

In this parameters are declared as WIDTH and DEPTH. These parameters are then used to define the width and depth of the memory. When this block of memory is called at a higher level these parameters can be overwritten through the higher module.  Lets discuss the parameter passing in next topic.
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