Chip Designing for ASIC/ FPGA Design engineers and Students

FULLCHIPDESIGN

Digital-logic Design...  Dream for many students… start learning front-end…

Topics @TYH :- 4G LTE Tutorial, Inside Smart-Phone, Cloud Computing

PICS

Direct link to return to Verilog Tutorial
http://www.fullchipdesign.com/verilog_tutorial.htm

Verilog Parameters

What are parameters?
The verilog parameters is a way of passing the constants to modules to overwrite there local constants for signal widths and depths (for memories).  This is done when the block is instantiated in top-level/higher-level module. Parameters also allows easy modifications of the code by changing the

Code snippet from the verilog sync ram page is below:
module mem_ram_sync(
   clk,
   rst,
   read_rq,
   write_rq,
   rw_address,
   write_data,
   read_data);

parameter WIDTH=8;
Parameter DEPTH=64;
Parameter LOG2D=6;

input             clk;
input             rst;
input             read_rq;
input             write_rq;
input    [LOG2D -1 :0]  rw_address;
input    [WIDTH - 1 :0]         write_data;
Output [WIDTH - 1:0]          read_data;

reg[7:0]     read_data;
integer out, i;

// Declare memory 64x8 bits = 512 bits or 64 bytes
/* Width of memory 8 bits and Depth of memory 64 locations */
reg [WIDTH-1:0] memory_ram_d [DEPTH-1:0];
reg [WIDTH-1:0] memory_ram_q [DEPTH-1:0];
// Code from here refer sync ram page
......
......
......
endmodule

In this parameters are declared as WIDTH and DEPTH. These parameters are then used to define the width and depth of the memory. When this block of memory is called at a higher level these parameters can be overwritten through the higher module.  Lets discuss the parameter passing in next topic.

Digital Design Resources

Clock Domain Crossing rtl & testbench example.
Rate change(asynchronous) FIFO design and fifo depth calculation.
Half-adder, Full-adder, 4-bit binary adder , adder-subtractor circuit, overflow with rtl & testbench. Binary Multiplier, Parity error TT
Arithmetic, logical, shift micro-operations. Stack organization, LIFO, RPN discussion.
VHDL rtl - Synchronous flip-flop, latch, shim to improve timing and counter example

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels.
Digital design Interview questions.
FPGA Interview. FPGA flow.
Guide to Graduate studies in US
Pipeline vs. Parallel processing.

Digital Logic fundamentals topics @ fcd
Digital basics tutorial
Binary number discussion, 1 and 2 complement discussion,
Binary arithmetic, Signed Magnitude, overflow, examples
Gray coding, Binary coded digital (BCD) coding, BCD addition
Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates
Discussion of Boolean Algebra with examples.
Duality Principle, Huntington Postulates, Theorems of Boolean Algebra - discussion with examples, Boolean Functions, Canonical and Standard Forms, Minterms and Maxterms
Sum of Minterms, Product of Maxterms or Canonical Forms,
Karnaugh map or K-map discussion 2, 3, ,4 5 var’s
Prime Implicant and Gate level minimization examples.

Misc. Verilog RTL examples:-

Binary to Gray Code conversion
File read write operations.
Clock domain crossing.
Half-adder, Full-adder, Tri-state buffer .
Verilog testbench to validate half-adder, full-adder and tri-state buffer.
VERILOG HOME

Arithmetic, logical and shift microoperations.
Binary to Gray code conversion
Readmemh, Readmemb. Random numbers
Memory Implementation - sync Ram and Testbench

K-map - 2,3,4,5 var & Prime Implicant discussion

Interview Questions. Main, FPGA, Digital Fundamentals

Media Gallery
Las Vegas
Grand Canyon
Alcatraz -the rock
San Francisco
Napa Valley
Los Angeles
17 Mile Drive
Golden Gate Bridge
Blog- Planning California Trip

Cloud Computing ?
Whenever a document or photo is uploaded on the web, a thread of cloud computing is active. Learn more from here.