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Step. Display the values from the text file on the compiler screen.
// Verilog code example for file operations
// module declaration
module file_readmemh;
/* Declare a array 4 word deep 20 locations wide for 20/4 = 5 hexadecimal words */
reg [19:0] data [0:3];
// initalize the hexadecimal reads from the vectors.txt file
initial $readmemh("vectors.txt", data);
/* declare an integer for the conditional
statement to read values from test file */
integer i;
/* read and display the values from the text file on the compiler screen */
initial begin
$display("rdata:");
for (i=0; i < 4; i=i+1)
$display("%d:%h",i,data[i]);
end
endmodule
Program. File operation using ‘readmemh’ for reading hexadecimal values from test files.
Step. Verilog code example for file operations
Step. Declare a array 4 word deep 20 locations wide for 5 hexadecimal values.
Step. Use ‘readmemh’ command to read hexadecimal values.
Step. Declare an integer to set a pointer to read values from test file.
Verilog readmemh function in rtl
Following program is discussed in this section
Results
Input => File vectors.txt =>
12abc 34def 1dead 2bee1
Output =>
0:12abc
1:34def
2:1dead
3:2bee1
Initial Statements for Test benches in Verilog.
Conditional ‘IF-
‘always’ block in verilog rtl.
Conditional ‘Case’ Statements.
Synchronous Counters implementation.
Verilog ‘readmemh’ code to read hex values.
Function declaration in verilog.
Verilog file read write operations.
Verilog testbench example.
Verilog Binary to Gray Code conversion example.
Verilog code for clock domain crossing.
Half-
Full-
Tri-
Verilog testbench to validate half-