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Verilog Tutorial.
SystemVerilog Topic - Localparam
Let’s discuss localparam in relation to previous topics of parameters and defparam statements.
To achieve best results from the  localparam avoid using the assignments with expressions containing parameters. Example below

Avoid following coding style using parameters and localparam.
Localparam prevents the values to be overwritten (directly) from outside the module. Once the variables are declared with ‘localparam’ the values stays constant. When the module is instantiated within another module the values can’t be passed for these data type.

Example code for using localparam:
ICG cell.

Assertions.

Concise assert.

Assert levels.

Chandle.

defparam.

Parameters.

Parameters Pass.

Defparam stms.

Localparam.

C:\iverilog\samples\mux_local.html module mux (A, B, C, Ctrl, Y);

 parameter  SZ = 3;
 parameter  CT = 2;
 localparam IN = CT**SZ;
 localparam OUT= CT**SZ;

input [IN-1:0] A, B, C;
input [CT-1:0] Ctrl;
output[OUT-1:0] Y;

always@(*)
begin
        case (Ctrl)
                0: Y = A;
                1: Y = B;
                2: Y = C;
                3: Y = A;
                default: Y =A;
        endcase

end
endmodule
C:\iverilog\samples\mux.v.html module mux (A, B, C, Ctrl, Y);

 parameter  CT = 4;
 localparam IN = 8;
 localparam OUT= 8;

input [IN-1:0] A, B, C;
input [CT-1:0] Ctrl;
output[OUT-1:0] Y;

always@(*)
begin
        case (Ctrl)
                0: Y = A;
                1: Y = B;
                2: Y = C;
                3: Y = A;
                default: Y =A;
        endcase

end
endmodule
LTE - Long Term Evolution topics from here
Interview Questions. Main, FPGA, Digital Fundamentals