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Verilog Initial stmts IF-ELSE Case stms Readmemh Function Testbench Binary to Gray Clock Crossing Half-adder Full-adder Tristate buffer Adder tb Counter_enable Blocking Operators Shift LSR Random Nos Sync RAM Verilog Tutorial

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Verilog Tutorial.
Half-Adder discussion with verilog rtl and testbench
Verilog RTL example for half-adder. Check the half-adder discussion in digital design section.

// Half Adder

module half_adder (in_x, in_y, out_sum, out_carry);

input  in_x;

input  in_y;

output out_sum;

output out_carry;

assign out_sum = in_x^in_y;

assign out_carry = in_x&in_y;

endmodule

Results:

1 Bit Half-Adder Results are discussed below

in_x = 0, in_y = 0, out_sum = 0, out_carry = 0

in_x = 0, in_y = 1, out_sum = 1, out_carry = 0

in_x = 1, in_y = 1, out_sum = 0, out_carry = 1

in_x = 1, in_y = 0, out_sum = 1, out_carry = 0

in_x = 1, in_y = 1, out_sum = 0, out_carry = 1

in_x = 0, in_y = 1, out_sum = 1, out_carry = 0

Half- adder test-bench code can be referred from here. Further topics full-adder, 4-bit binary adder, 4-bit binary adder-subtractor.
Digital Logic fundamentals -
Access the digital fundamental tutorial from here
 Binary number discussion, complement discussion, Binary arithmetic, Signed Magnitude and examples, Gray coding, BCD coding, BCD addition, Digital logic gates, Discussion of Boolean Algebra, Duality Principle, Huntington Postulates, Theorems of Boolean Algebra - discussion, Boolean Functions, Canonical and Standard Forms, Minterms and Maxterms discussion, Sum of Minterms, Product of Maxterms or Canonical Forms, Karnaugh map or K-map discussion 2, 3, ,4 and 5 var’s , Prime Implicant and Gate level minimization examples.
RF basics - RF fundamentals discussion
 SignaltoNoise(SNR), NoiseFactor(F), NoiseFigure(NF), Dynamic Range (DR), Minimum Detectable Signal (MDS),
Intermodulation (IM) distortion, Second order (IP2) & Third order  (IP3) intermodulation products, IP3 (Third Order Intercept) plot
 Desensitization, Cross-modulation, Spurious outputs, Gain control, Noise
Other sections of interest on FCD
Interview Questions. Main, FPGA, Digital Fundamentals