Half-Adder discussion with verilog rtl and testbench.

Verilog RTL example for half-adder. Check the half-adder discussion in digital design section.

module half_adder (input in_x, input in_y,
output out_sum, output out_carry); // XOR for SUM assign out_sum = in_x^in_y; // AND gate for Carry assign out_carry = in_x&in_y; endmodule

The output of test-bench is shown below.

LTE - 4G Wireless Technology

Digital fundamentals.

Interview Questions.

To generate this output we will need to instantiate this code in the test-bench example from here.

1 Bit Half-Adder Results are discussed in tabular form below, first two columns are for inputs and the last two columns are for outputs:

in_x = 0, in_y = 0, out_sum = 0, out_carry = 0

in_x = 0, in_y = 1, out_sum = 1, out_carry = 0

in_x = 1, in_y = 1, out_sum = 0, out_carry = 1

in_x = 1, in_y = 0, out_sum = 1, out_carry = 0

in_x = 1, in_y = 1, out_sum = 0, out_carry = 1

in_x = 0, in_y = 1, out_sum = 1, out_carry = 0

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