Half-Adder discussion with verilog
rtl and testbench.
Verilog RTL example for half-
module half_adder (input in_x, input in_y, output out_sum, output out_carry); // XOR for SUM assign out_sum = in_x^in_y; // AND gate for Carry assign out_carry = in_x&in_y; endmodule
The output of test-bench is shown below.