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Initial stmts.

IF-ELSE.

Case stms.

Readmemh.

Function.

Testbench.

Binary to Gray.

Cllock Crossing.

Half-adder.

Full-adder.

Tristate buffer.

Adder tb.

Counter_enable.

 Blocking.

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Half-Adder discussion with verilog rtl and testbench
Verilog RTL example for half-adder. Check the half-adder discussion in digital design section.

// Half Adder

module half_adder(in_x, in_y, out_sum, out_carry);

input  in_x;

input  in_y;

output out_sum;

output out_carry;

assign out_sum   = in_x^in_y;

assign out_carry = in_x & in_y;

endmodule

Results:

----------------------

1 Bit Half-Adder

----------------------

in_x = 0, in_y = 0, out_sum = 0, out_carry = 0

in_x = 0, in_y = 1, out_sum = 1, out_carry = 0

in_x = 1, in_y = 1, out_sum = 0, out_carry = 1

in_x = 1, in_y = 0, out_sum = 1, out_carry = 0

in_x = 1, in_y = 1, out_sum = 0, out_carry = 1

in_x = 0, in_y = 1, out_sum = 1, out_carry = 0

Half- adder test-bench code can be referred from here  
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