Verilog constant propagation Synthesis.

Constant Propagation is an optimization technique employed by synthesis tools to minimize hardware implementation.

This is achieved by optimizing away the logic for which parameters are configured to keep it disabled. This technique is not limited to module boundaries and the hardware can be optimized away both inside and outside. This two way optimization depends on the output port dependencies on the parameter configurations for the module.

 

Lets discuss it in more details with an example below.

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~\Documents\fullchip\python\mysite\webpages\templates\webpages\test.v.html 
module DUT (
    in1, in2, out1, out2);

    // parameter declaration
    parameter ENABLE = 0;
    // ports
    input in1, in2;
    output out1, out2;
    // wires
    wire w_gate1, w_gate2;

    // logic

    assign w_gate1 = (ENABLE == 1) ? in1 : 1'b0;
    assign w_gate2 = (ENABLE == 1) ? in2 : 1'b0;

    assign out1 = w_gate1 & w_gate2;
    assign out2 = w_gate1 ^ w_gate2;

endmodule

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Explanation of the above code is below.

In above code when parameter Enable is set to 0, all internal logic and outputs will get optimized away by the Synthesis tools. This is done to save area on the hardware. In order to better understand constant propagation during synthesis its important to have good knowledge of parameters in Verilog RTL. If you want to review parameter topics then refer following links.

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