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Register transfer level (RTL) is used to create a high level description of a synchronous digital circuit.

If  - Else are used to generate priority logic in RTL. It can be used in both synchronous and combinational logic.

Synchronous priority logic generation

In this scenario entire logic within always block is executed in parallel with respect to a reference clock. ‘<=‘ operator is called non-blocking operator.

In this scenario the logic is implemented independent to clock. All statements in this block are executed in sequence. ‘=‘ is called blocking operator.

reg r_packet_in;

reg packet_in;

always@(posedge clk_1fs or negedge rst_n)

begin

    if (!rst_n) begin

        r_packet_in <= 'b0;

    end

    else begin

        r_packet_in <= packet_in;

    end

end

Check the complete implementation of the above logic in verilog testbench example.

Conditional if statements in Verilog