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Digital Basics Tutorial.

Register transfer level (RTL) is used to create a high level description of a synchronous digital circuit.

If -else construct in RTL is used to generate priority logic. This construct prevents parallel processing in hardware.  

If, else if and else constructs are used in both synchronous and combinational logic for priority generation.

Synchronous priority logic generation

In this scenario entire logic within always block is executed in parallel with respect to a reference clock. ‘<=‘ operator is called non-blocking operator.

BLOCKING OPERATOR: In this scenario the logic is implemented independent to clock. All statements in this block are executed in sequence. ‘=‘ is called blocking operator.

module ();

— - - -  declare inputs and outputs

reg r_packet_in;

reg packet_in;

always@(posedge clk_1fs or negedge rst_n)

begin

    if (!rst_n) begin

        r_packet_in <= 'b0;

    end

    else begin

        r_packet_in <= packet_in;

    end

End

— - -

endmodule

Check the complete implementation of the above logic in verilog testbench example.

Conditional if-else construct in Verilog

Home Verilog Initial stmts IF-ELSE Case stms Readmemh Function Testbench Binary to Gray Clock Crossing Half-adder Full-adder Tristate buffer Adder tb Counter_enable Blocking Operators Shift LSR Random Nos Sync RAM Verilog Tutorial
~\Desktop\verilog_code\ifcode.v.html
    module ifcode (
            in_a,
            in_b,
            in_c,
            in_ctrl,
            out_d
    );
    // Define inputs/outputs
    input  in_a;
    input  in_b;
    input  in_c;
    input[1:0]  in_ctrl;
    output out_d;
    // Use of if statement. 
    always@(*)
    begin
      if (in_ctrl == 2'b00)
         out_d = in_a;
      else if (in_ctrl == 2'b01)
         out_d = in_b;
      else
         out_d = out_c;
    end
    endmodule
    
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