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Home Verilog Initial stmts IF-ELSE Case stms Readmemh Function Testbench Binary to Gray Clock Crossing Half-adder Full-adder Tristate buffer Adder tb Counter_enable Blocking Operators Shift LSR Random Nos Sync RAM Verilog Tutorial
Verilog testbench to generate random numbers and use of $fdisplay to store it in a text file.
Generating random numbers and $fdisplay in Verilog testbench.
~\Desktop\FCD\downloads\fc_v\random_fc.v.html // Test Bench for generating random numbers
module random_tb ();

integer seed;
integer out;
integer i ;

initial begin
  out = $fopen("rand.vec","w");
  $fdisplay(out, "seed = %h, 1st random number in hexadecimal = 0x%h", seed, $random(seed));
  $fdisplay(out, "seed = %h, 2nd random number in hexadecimal = 0x%h", seed, $random(seed));
  $fdisplay(out, "seed = %h, 3rd random number in hexadecimal = 0x%h", seed, $random(seed));
  $fdisplay(out, "seed = %h, 4th random number in hexadecimal = 0x%h", seed, $random(seed));
  $fdisplay(out, "seed = %h, 5th random number in hexadecimal = 0x%h", seed, $random(seed));
end

endmodule
Results of verilog random generation are displayed in ‘rand.vec’ file below.
seed = 23980634, 1st random number in hexadecimal  = 0x12153524
seed = 92153206, 2nd random number in hexadecimal = 0xc0895e81
seed = 40895ccf,  3rd random number in hexadecimal  = 0x8484d609
seed = 0484d4c4, 4th random number in hexadecimal  = 0xb1f05663
seed = 31f054f5,  5th random number in hexadecimal  = 0x06b97b0d
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