Operations - conditionals, concatenation and replicate.

Category Name Symbol Implementation
Concatenation Concatenation { , } Append two values in one register.
      Example:- R3[5:0] = {R1[2:0],R2[2:0}
Replication Replication {r{p}} Where value of p is replicated r times
Conditional Conditional (condition)? V1 : V2 If condition is true then assign value V1 otherwise V2.

Verilog Operator Precendence.

Bitwise - Operation on individual bits of registers. Also discussed is the verilog code implementation. 

Category Name Symbol Implementation
Bitwise - in Verilog Negation ~ 1’s complement
  Bitwise OR | Bitwise OR
  Bitwise AND & Bitwise AND
  Bitwise XOR ^ Bitwise XOR
  Bitwise NAND ~& Bitwise NAND
  Bitwise NOR ~| Bitwise NOR
  Bitwise XNOR ~^ Bitwise XNOR
  Bitwise XNOR ^~ Bitwise XNOR

Binary Aritmetic Operators - Each bit of the register is individually operated with corresponding bit in other register.  
 
Name Symbol Implementation
Addition + Addition of two registers
Subtraction - 2's complement subtraction
Multipliction * Multiplication of two registers
Exponent ** Exponent supported in Verilgo 2001
Division / Division of two registers.
 
Logical - Operation on registers as logical statements True and false. These are primarily used in conditional statements like ‘IF’, ‘ELSE IF’
 
Category Name Symbol Implementation
Logical AND && AND - True when all operands are TRUE
  OR || OR - True when any one operand is TRUE
  NOT ! Not is like a inverter.
       
Comparison Greater than > True when arithmetic value of one register is greater than the other register in comparison.
  Less than < True when arithmetic value of one register is less than the other register in comparison.
  Greater than or equal >= True when arithmetic value of one register is greater than or equal to the other register in comparison.
  Greater than or equal <= True when arithmetic value of one register is less than or equal to the other register.
  Equal to == ‘==’ Logical equality excluding Tristate values (‘bX).
    === ‘===’ Logical equality including Tristate values or ‘bX.
  Not equal != or !== ‘!=’ Logical in-equality excluding Tristate values or ‘bX.
      ‘!==’ Logical in-equality including Tristate values or ‘bX.

LTE - 4G Wireless Technology

Digital fundamentals.

Interview Questions.

Shift - Shift values of registers and store the new value.

Category Name Symbol Implementation
Shift and store Logical Right Shift >> Shift the contents of register right and drop the bits.
  Logical Left Shift << Shift the contents of register left and drop the bits.
  Arithmetic Right Shift >>> Supported Verilog 2001 onwards. Shift the contents of register right and store the bits in MSB bits.
  Arithmetic Left Shift <<< Supported Verilog 2001 onwards. Shift the contents of register left and store the bits in lsb bits.

Tutorials @fullchipdesign.com

Verilog Tutorial.

LTE Tutorial.

Memory Tutorial.

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