Chip Designing for ASIC/ FPGA Design engineers and Students

FULLCHIPDESIGN

Digital-logic Design...  Dream for many students… start learning front-end…

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/*Function declaration and calling a function is discussed in this section.*/

reg [5:0] counter_binary, counter_binary_reg, counter_gray, counter_gray_reg;
integer count, file_wr;

/*Function to get Gray code from Binary code*/

function[5:0] binary2gray ;
   input[5:0] value;
   integer i;

   begin
        binary2gray[5] = value[5];
       for (i=5; i>0; i = i - 1)
           binary2gray[i-1] = value[i] ^ value[i - 1];
   end
endfunction

//Calling a function
always @(*)
begin
   counter_binary = counter_binary_reg;
  counter_gray = binary2gray(counter_binary_reg);
end

Function declaration and use in Verilog.