Verilog Counter & testbench with synchronous enable control.

Counter implementation and use of synchronous signal ‘count_en’ to disable the counter. Lets start with simple counter code in rtl.

// Just the code snippet below.

always @(posedge clock or negedge reset)

begin

if (~reset) cnt_C <= 0;

else cnt_C <= cnt_C + 1;

end

Next lets review code to allow the counter to get enable/disable through additional signals. We will use asynchronous reset here in the example. Also test-bench is provided for reference.

LTE - 4G Wireless Technology

Digital fundamentals.

Interview Questions.

~\Documents\fullchip\python\mysite\webpages\templates\webpages\test.v.html 
module tb_counter();

reg clk_1fs;

reg rst_n;

reg [3:0] r_count;

reg [3:0] count;

reg count_en;

initial begin

     clk_1fs = 0;

     rst_n = 0;

     #100 rst_n = 1;

     forever begin

         #10 clk_1fs = 1;

         #10 clk_1fs = 0;  end

end

always@(posedge clk_1fs or negedge rst_n) begin

    if (!rst_n) begin

        r_count <= 'b0;

        count_en <= 'b0; end

    else begin

        r_count <= count; end

end

always@(*) begin

   count = r_count;

   if (r_count < 15 && !count_en)

 begin

         count = r_count + 1; end

  else if (r_count == 15) begin

        count_en = 1;

        count = 15; end

  else count = 15; end

endmodule

Tutorials @fullchipdesign.com

Verilog Tutorial.

LTE Tutorial.

Memory Tutorial.

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