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Digital Basics Tutorial.
Verilog Counter & testbench - with synchronous enable/disable control

module tb_counter();

 

reg clk_1fs;

reg rst_n;

reg [3:0] r_count;

reg [3:0] count; 

reg count_en;

 

initial begin 

     clk_1fs = 0; 

     rst_n = 0;

     #100 rst_n = 1;

     forever begin

         #10 clk_1fs = 1;

         #10 clk_1fs = 0;

          end

end

 

always@(posedge clk_1fs or negedge rst_n)

Begin

    if (!rst_n)

   begin

        r_count <= 'b0;

        count_en <= 'b0;  

    end

    else

   begin 

        r_count <= count;

   end

end

 

always@(*)

begin 

   count = r_count;

   if (r_count < 15 && !count_en) 

 begin

         count = r_count + 1; 

 end

  else if (r_count == 15)

 begin

        count_en = 1;

        count = 15;

 end

  else count = 15;

end 

 

endmodule

 

Counter implementation and use of synchronous signal ‘count_en’ to disable the counter.  Also the following code will allow the counter and counter enable signals to get  asynchronously reset with external input or test-bench generated signal rst_n. Following code is implemented within test-bench.   

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Interview Questions. Main, FPGA, Digital Fundamentals
Free running Verilog counters code with asynchronous reset and synchronous reset.