System Verilog (SV) `Arrays`.

An array is a resource of variables contained in a assigned space and designated by one name. The variables are then noted as elements of the arrays which can be accessed independently.

SystemVerilog supports array of following types fixed size, dynamic and associative. Multiple dimensions are only allowed on fixed size arrays.

So dynamic and associative arrays are only added in System Verilog.

Next we will discuss about Packed and un-packed arrays with examples.

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Example:

bit [3:0] p_array; // packed array

real up_array [3:0]; // unpacked array

Packed array representation:

So bit width in “p_array” is declared before the array name.

Unpacked array representation:

In case of “up_array”, bit width is declared after the array name.

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