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Verilog Tutorial.
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System Verilog Functions. Verilog functions here.
In System Verilog, functions have added functionality. It now supports “void” function calls and also allow formal arguments. Lets discuss these enhanced features next.  
ICG cell Assertions Concise assert Assert levels Chandle defparam Parameters Parameters Pass Defparam stms Localparam Constant Pass Alias Array Functions always

VOID functions. What is a void function? The system verilog functions are declared void when no return value is required. In our example we are calling function “testprint” to print a value passed as input integer.





function void testprint(int i);


Non-void system verilog functions. Example code below:

function [3:0] reverse_order (input[3:0] a, output[3:0] b );

integer i;

// No need of begin/end in SystemVerilog

for (i=0; i<4; i=i+1)

    b = a[3-i];



So from example above we noticed that SystemVerilog doesn’t mandate begin and end for coding logic.

SystemVerilog: Parameters passing, defparam & localparam, Alias, Array, Assertions


How are Function return used in System Verilog. For type (or non-void) functions, a value can be returned by adding a final line in code with “return abcd”.  Where abcd is always associated with return and its the expression required to return a value with function call. Example below:



function [4:0] simple_adder_with_carry (input [3:0] x,y);

return x + y;



So SV compilers by default interprets all statements within function and endfunction as sequential.

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4. F(x,y,z) =     (0,1,2,3,4,5,6,7) - Minimization from here.
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Parameters passing, defparam & localparam

Alias, Array, Assertions