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C:\iverilog\samples\memory_ram_sync_param.v.html // Test Bench for memory modeling
module memory_tb ();
reg clk, rst; 

reg      read_rq;
reg      write_rq;
reg[5:0] rw_address;
reg[31:0] write_data;
wire[31:0] read_data;
reg [6:0] q_cnt;

integer seed;
integer out, rout;

initial 
begin
    clk = 0;
   forever #10 clk = ~clk;
end

initial begin 
    rst = 0;
    # 50 rst = 1;
end

always @(posedge clk or
    negedge rst)
begin
    if (!rst)
    begin 
     q_cnt <= 0;
     write_data <= 'b0;
     out = $fopen("mem_ram.vec","w");
     rout = $fopen("mem_ram_read.vec","w");
    end
    else
    begin
        if (q_cnt < 65)
        begin
            q_cnt <= q_cnt+1;
            write_data <= $random(seed) & 'hFFFF;
            read_rq <= 0;
            write_rq <= 1;
            rw_address <= q_cnt;
            #10 $fdisplay(out, "Address::%d:: %b :: -- contents in hex %h", rw_address, write_data, write_data);
        end
        else
        begin
            q_cnt <= q_cnt;
            write_data <= write_data;
            rw_address <= $random(seed) & 'h3F;
            read_rq <= 1;
            write_rq <= 0;
            #10 $fdisplay(rout,"Address::%d:: %b :: -- read contents in hex %h", rw_address, read_data, read_data);
        end
    end
end

defparam u_dut_ram.WIDTH = 32;
defparam u_dut_ram.DEPDTH = 64;
defparam u_dut_ram.LOG2DEPTH = 6;

mem_ram_sync u_dut_ram
(
    .clk(clk),
    .rst(rst),
    .read_rq(read_rq),
    .write_rq(write_rq),
    .rw_address(rw_address),
    .write_data(write_data),
    .read_data(read_data)
);

endmodule

module mem_ram_sync(
    clk,
    rst,
    read_rq,
    write_rq,
    rw_address,
    write_data,
    read_data
);

parameter WIDTH = 8;
parameter DEPTH = 64;
parameter LOG2DEPTH = 6;

input           clk;
input           rst;
input           read_rq;
input           write_rq;
input[LOG2DEPTH-1:0]      rw_address;
input[WIDTH-1:0]      write_data;
output[WIDTH-1:0]     read_data;

reg[WIDTH-1:0]     read_data;

integer out, i;

// Declare memory 64x8 bits = 512 bits or 64 bytes
reg [WIDTH-1:0] memory_ram_d [DEPTH-1:0];
reg [WIDTH-1:0] memory_ram_q [DEPTH-1:0];

// Use positive edge of clock to read the memory
// Implement cyclic shift right
always @(posedge clk or
    negedge rst)
begin
    if (!rst)
    begin
        for (i=0;i<64; i=i+1)
            memory_ram_q[i] <= 0;
    end
    else
    begin
        for (i=0;i<64; i=i+1)
             memory_ram_q[i] <= memory_ram_d[i];
    end
end

/* Memory read and write operations */
always @(*)
begin
    for (i=0;i<64; i=i+1)
        memory_ram_d[i] = memory_ram_q[i];
    if (write_rq && !read_rq)
        memory_ram_d[rw_address] = write_data;
    if (!write_rq && read_rq)
        read_data = memory_ram_q[rw_address];
end
 
endmodule
Verilog defparam statements
Alternate way of passing parameters is to use a defparam statements with hierarchical names. These statements are used in the higher level module where a parameterized block of code is instantiated. Example of defparam statements are discussed here.   
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