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Initial Statements in Verilog
Initial statements with examples are discussed in this section. Also discussed are clocks and resets generation logic using forever loop and not operator.
Statements within initial block are used in Verilog for generating test signals, example clocks, resets etc.
Initial statements can’t be synthesized because actual behavior of hardware is difficult to model using fixed delays. These statements are used only for testbench purposes and to initialize the values at zero simulation time.
Example code:
// Register declarations
reg clk_1fs;
reg clk_1fs_d;
reg rst_n;
// Use of initial statement to generate clocks 1fs and 1fs_d
initial begin
clk_1fs = 0;
clk_1fs_d = 0;
rst_n = 0;
#100 rst_n = 1;
forever begin
#10 clk_1fs = 1;
#11 clk_1fs_d = 1;
#10 clk_1fs = 0;
#11 clk_1fs_d = 0;
end
end
end
reg clk;
reg rstn;
// Initial block to generate clock and reset
initial
begin
clk = 0; rstn = 0; #100 rstn = 1;
forever begin
#10 clk = !clk; end
end