Binary Multiplication disucssion for two, 2 bits registers. 

Binary multiplier is very similar to decimal multiplication. The implementation is discussed in details with diagram and examples.

Lets start the discussion with an example of two bit binary numbers. To explain the carry lets use both numbers as 3. 
A = 2‘b11 (In verilog 2‘b stands for 2 bits wide binary number)
B = 2‘b11

4’b1001 = 9 in decimal is equivalent to binary multiplication of 2’b11x2’b11.

Binary multiplier.

Circuit Level Implementation of multiplier is shown below.

LTE - 4G Wireless Technology

Digital fundamentals.

Interview Questions.

Binary multiplier.

Total Gates used in Multiplier circuit.

The block diagram implementation of multiplier shows that the circuit requires four AND gates and two Half-adder (two-gates each).

Other topics of intereset at Fullchipdesign.

Clock Domain Crossing Discussion with rtl & testbench example.

Rate change(asynchronous) FIFO design and fifo depth calculation.

Half-adderFull-adder, 4-bit binary adder , adder-subtractor circuit, 

Overflow with rtl & testbench

Binary Multiplier,

Parity error TT

Arithmeticlogicalshift micro-operations.

Stack organizationLIFO, RPN discussion.

VHDL rtl - Synchronous flip-floplatchshim to improve timing and counter example

RTL coding guidelinesICG cell, Assertions$assertkilllevels.

Digital design Interview questions. FPGA Interview. FPGA flow.

Pipeline vs. Parallel processing.

Guide to Graduate studies in US



Verilog Tutorial.

LTE Tutorial.

Memory Tutorial.

Hope you liked! this page. Don't forgot to access relevant previous and next sections with links below.