VLSI Synthesis for Digital Design.
Digital design Synthesis for
VLSI applications: Its a EDA technique to map high level
behavioral designs into gates. Behavioral designs are coded in Register Transfer Level languages like Verilog, VHDL etc.
Introduction to VLSI - Discussed on this page.
Role of synthesis in digital chip design.
Discussion on various synthesis stages.
Design constraints for digital design.
Constant Propagation is an optimization technique employed by
synthesis tools to minimize hardware implementation.
As you understand a Flop to Flop path is
critical for timing, lets discuss setup time, hold time and metastability.
Now lets understand clock domain crossing across
two asynchornous clock domains.
PLL's discssion - Phase Locked Loop. Follow this section for PLL’s for ASIC, FPGA configuration.
CMOS in VLSI - Parasitics, Crosstalk and Ground Bounce.