Asynchronous FIFO design and
calculate the Depth of the FIFO.
FIFO design requirements.
FIFO is a First in First Out is used to buffer data in Digital Systems. Requirement of FIFO arises when the reads are slower than the writes.
Calculating FIFO parameters:
In order to calculate the depth of the FIFO, first we need to understand the worst case scenario of that particular design. Here is an example of a worst case scenario:-
Write side of FIFO:
Write clock frequency = 15 MHz (clk_wr)
Maximum size of the Burst = 100 bytes (burst_width)
Delay between writes in a burst = 1 clock cycle (wr_delay)
Read side of FIFO:
Read clock Frequency = 10 MHz (clk_read)
Delay between reads = 2 clock cycles (rd_delay)
Six step approach to calculate FIFO
Depth of the FIFO = 100 – 66.7/2 = 100 – 33.35 = 66.65 = 67