# Asynchronous FIFO design and `calculate` the Depth of the FIFO.

Understanding `FIFO` design requirements.

FIFO is a First in First Out is used to buffer data in Digital Systems. Requirement of FIFO arises when the reads are slower than the writes.

Calculating FIFO parameters: In order to calculate the depth of the FIFO, first we need to understand the worst case scenario of that particular design.  Here is an example of a worst case scenario:- example below.

Write side of FIFO:

Write clock frequency = 15 MHz (clk_wr)

Maximum size of the Burst = 100 bytes (burst_width)

Delay between writes in a burst = 1 clock cycle (wr_delay)

Delay between reads = 2 clock cycles (rd_delay)

Six step approach to calculate FIFO `parameters.`

Step1:- FIFO Width = 8 (1 byte = 8 bits worth of data at each buffer location)

Step2:- Assume depth of FIFO to capture the complete buffer = 100 (maximum size of burst)

Step3:- No of write clock cycles for writing 100 locations in FIFO = 100 @ clk_wr

Step4:- Time taken to write 100 locations = 100/(15*10^6) = 6.67 us

Step5:- No of reads during 6.67 us = (6.67 us) * 10 * 10^6 = 66.7 @ clk_read (approx 67)

Depth of the FIFO = 100 – 66.7/2 = 100 – 33.35 = 66.65 = 67

FIFO DEPTH calculation formula is summarized in next topic.

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Digital fundamentals.

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Other topics `of intereset at Fullchipdesign.`

``` Clock Domain Crossing Discussion with rtl & testbench example. Rate change(asynchronous) FIFO design and fifo depth calculation. Half-adder, Full-adder, 4-bit binary adder , adder-subtractor circuit,  Overflow with rtl & testbench.  Binary Multiplier, Parity error TT Arithmetic, logical, shift micro-operations. Stack organization, LIFO, RPN discussion. VHDL rtl - Synchronous flip-flop, latch, shim to improve timing and counter example RTL coding guidelines. ICG cell, Assertions, \$assertkill, levels. Digital design Interview questions. FPGA Interview. FPGA flow. Pipeline vs. Parallel processing. ```

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