// Verilog Test Bench for half-adder, full-adder and tri-state buffer
module tb_fulladder();
reg r_in_x;
reg r_in_y;
reg r_carry_in;
wire out_sum;
wire out_sum_fa;
wire out_carry;
wire out_carry_fa;
reg w_enable;
wire w_output_x;
initial begin
$display("------------\n1 Bit Half-Adder\n----------------------\n");
$monitor("in_x = %b, in_y = %b, out_sum = %b, out_carry = %b", r_in_x, r_in_y, out_sum, out_carry);
$display("----------------------\n1 Bit Full-Adder\n----------------------\n");
$monitor("in_x = %b, in_y = %b, carry_in = %b, out_sum_fa = %b, out_carry_fa = %b", r_in_x, r_in_y, r_carry_in, out_sum_fa, out_carry_fa);
$display("----------------------\nTri-State Buffer\n----------------------\n");
$monitor("input_x = %b, enable = %b, output_x = %b", r_in_x, w_enable, w_output_x);
// Generation of stimulus
r_in_x = 0; r_in_y = 0; r_carry_in = 0; w_enable= 0; # 10 r_carry_in= 1;
# 10 r_in_x = 0; # 10 r_in_y = 1; # 10 r_carry_in = 0; # 10 r_carry_in = 1;
# 10 r_in_x = 1; # 10 r_in_y = 0; # 10 w_enable = 1; # 10 r_carry_in = 0;
# 10 r_carry_in = 1; # 10 r_in_x = 1; # 10 r_in_y = 1; # 10 r_carry_in = 0;
# 10 r_carry_in = 1; # 10 r_in_x = 0; # 10 r_in_y = 1; # 10 r_carry_in = 0;
# 10 r_carry_in = 1; # 10 w_enable = 1;
End
// Half-adder instantiation
half_adder u_half_adder
(.in_x(r_in_x), .in_y(r_in_y),
.out_sum(out_sum),
.out_carry(out_carry));
// Full-adder instantiation
full_adder u_fulladder
( .in_x (r_in_x),
.in_y (r_in_y),
.carry_in (r_carry_in),
.sum_out (out_sum_fa),
.carry_out(out_carry_fa));
// Tri-state buffer instantiation
tristate_buffer u_tristate_buffer
( .input_x (r_in_x),
.enable (w_enable),
.output_x (w_output_x));
endmodule
Check the RTL code for the DUT’s from here
Half-adder RTL, Full-adder RTL and tri-state buffer RTL