Verilog Tutorial

This is a systematic section to provide details on Verilog rtl coding. Witihn fullchipdesign you can discover several pages to go deeper into logic fundamentals.  

  1. Foundation of RTL design.
    1. Introduction to Verilog RTL under Verilog tutorial.
    2. Verilog Operators.

  2. Very first statements in verilog.
    1. Initial Statements in verilog.

  3. Starting with a simple test-bench.
    1. Clock and Reset generation discussion in Verilog Tutorial.
    2. Random number and use of $fdisplay.
    3. File Operations - $fopen, $fclose, $fdisplay, $fscanf
    4. Read binary or hex format files - $readmemh, $readmemb.
    5. Testbench example - complete code.

  4. Introduction to blocking vs. non-blocking.
    1.  Blocking vs. Non-blocking Statements. 

  5. Logic constructs.
    1. Conditional Statements & ‘always’ block.
    2. CASE statement implementation.
    3. Shift micro-operations and use in rtl.
    4. FOR Loop use under Verilog tutorial examples.

  6. Memory instantiation and validation. 
    1. Memory implementation and test-bench.
    2. Memory - Synchronous RAM implementation.
    3. Verilog Generate for memory instances.

  7. Disucssion on Assertions.
    1. Assertions in Verilog Introduction and few examples.

  8. Parameters passing.
    1. Parameters passing.
    2. Defparam statements.

  9. Signed RTL Design.
    1. Signed rtl design.

Discuss another blog on verilog rtl examples here. 

LTE - 4G Wireless Technology

Digital fundamentals.

Interview Questions.


Verilog Tutorial.

LTE Tutorial.

Memory Tutorial.

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