RTL (Register Transfer Level).
Verilog and System Verilog are programming languages designed to code hardware at register transfer level. The digital hardware consists of concurrent and sequential events. A synchronous digital circuit is modeled with following considerations:
- A circuit consists of sequential & parallel events.
- Interim results are stored in registers.
- Registers are generally implemented as D Flip Flops.
- Data is transferred between registers which are synchronous to each other.
Before starting RTL coding its
good to visit coding guidelines section.
verilog and system verilog rtl code below.