Verilog - RTL (Register Transfer Level).

Verilog and System Verilog are programming languages designed to code hardware at register transfer level. The digital hardware consists of concurrent and sequential events. A synchronous digital circuit is modeled with following considerations:

  • A circuit consists of sequential & parallel events.
  • Interim results are stored in registers.
  • Registers are generally implemented as D Flip Flops.
  • Data is transferred between registers which are synchronous to each other.

Before starting RTL coding its good to visit coding guidelines section

Verilog Tutorial for systematic learning is covered here.

Practice verilog and system verilog rtl code below.

LTE - 4G Wireless Technology

Digital fundamentals.

Interview Questions.

Verilog operators - Building blocks of Verilog. Follow topics in verilog tutorial to learn the language.
Verilog Initial Statements -  Used in Test benches for generating stimulus (clocks, resets, etc).
Conditional Statements - IF-ELSE’ statement and use in ‘always’ block‘case’ statement 
Synchronous Counters. Implementation example.
⇒ Readmemh - ‘readmemh’ code to read hex values in a test-bench.
Functions and its call in verilog tutorial.
⇒ Verilog Test-bench FILE read write operations.
⇒ Verilog testbench example. More examples are presented online under Verilog tutorial. 
⇒ Verilog Binary to Gray code conversion example.
Verilog code for CDC clock domain crossing.
Half-adderFull-adderTri-state buffer implementation in verilog. 
Testbench to validate half-adder, full-adder and tri-state buffer.


Verilog Tutorial.

LTE Tutorial.

Memory Tutorial.

⇒ Verilog counter enable logic. Tesbench to generate counter and synchronous enable logic.
Verilog difference between blocking and non-blocking statements.
Shift micro operations verilog rtl code and simulation results. 
  → logical shift right (lsr).
  → logical shift left (lsl) .
  → circular shift right (csr)
  → circular shift left (csl).
Random number generation in test-bench and use of $fdisplay.
Memory - synchronous RAM implementation and test-bench.
Signed rtl design - Required for digital signal procesing design.
Assertions discussion.
  → Assertions levels in System Verilog (SV).
  → Assertions hierarchy in SV.
  → 'Chande' for DPI-C in SV.
⇒ Constant propagation in Verilog.
⇒ Parameters and defparam in Verilog.
⇒ Verilog Parameter passing.
⇒ Verilog Localparam usage in rtl.
⇒ Alias in System Verilog (SV).
⇒ Arrays in System Verilog (SV).
⇒ Functions in SV. Discuss VOID and Non-Void functions.

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