Parity Generation and Checking.

In digital communications, a large amount of data is transmitted and received across various mediums. Mostly during the transfers some noise gets added to the data and makes it difficult to recover signal. 

To Make the data recovery easier an extra bit is appended to the binary (0,1) message to make the ‘logic 1’ count even or odd. This extra bit is known as parity bit and used for error detection. 
Parity systems are implemented on both transmitters and receivers.

The transmitter is responsible for generating the parity bit.

The receiver is responsible for detecting the message including the parity bit.

If message doesn’t meet the parity check an error flag is generatedand transmitter is requested to re-transmit the packet.

LTE - 4G Wireless Technology

Digital fundamentals.

Interview Questions.

Circuit Level implementation of parity generator and parity checker.

The block diagram implementation of generator and checker shows that the circuit requires 2 XOR gates at the parity generation side of transmitter and 3 XOR gates at the receiver side of parity checker. 

Possible Verilog code here 

module ...
priority_output = C^(A^B);
parity_rx_error = (prioirty_output^C)^(A^B);

Access Truth tables of parity generation and parity checker from here.

Parity Generation and Checking


Verilog Tutorial.

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