Memory sub-system, IO control & Bus sub-system.

The memory unit is a critical component of digital computing where data needs to be read, processed and stored frequently. Following block diagram shows the connectivity of CPU, memory and I/O unit through bus connections. As the requirements of storage capacity increases with the processing power of CPU, we need to design systems with several levels of storage. These levels of hierarchy requires several tradeoffs on design platform. One such tradeoff is with distance of the memory from CPU. As the distance increases, the delay on data transfer increases which in-turn reduces overall performance of the device reduces.
Block diagram below shows the connectivity of CPU, memory and I/O unit through bus connections. Memory needs to be organized around CPU and central bus-sub system. Central bus-subsystem is also know as memory bus-subsystem and needs to handle all data communication in-between cpu and main memory.

Memory Organization

LTE - 4G Wireless Technology

Digital fundamentals.

Interview Questions.

We have already covered CPU in previous section. Lets discuss the memory sub-system here.
Computer memories are divided into Cache memory, main memory and secondary memory. Where Cache is the fastest and closest to processor. Cache memory is also the smallest memory. Secondary memory is the slowest, furthest from processor and largest in size.


Memory Organization

In next section we will discuss Cache memory organization. NEXT



Verilog Tutorial.

LTE Tutorial.

Memory Tutorial.

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